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FDS6685のメーカーはFairchild Semiconductorです、この部品の機能は「P-Channel Logic Level PowerTrenchTM MOSFET」です。 |
部品番号 | FDS6685 |
| |
部品説明 | P-Channel Logic Level PowerTrenchTM MOSFET | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとFDS6685ダウンロード(pdfファイル)リンクがあります。 Total 8 pages
March 1999
PRELIMINARY
FDS6685
P-Channel Logic Level PowerTrenchTM MOSFET
General Description
This P-Channel Logic Level MOSFET is produced using
Fairchild Semiconductor's advanced PowerTrench process
that has been especially tailored to minimize on-state
resistance and yet maintain superior switching
performance.
These devices are well suited for low voltage and battery
powered applications where low in-line power loss and
fast switching are required.
Applications
• Battery protection
• Load switch
• Motor drives
Features
• -8.8 A, -30 V. RDS(ON) = 0.020 Ω @ VGS = -10 V
RDS(ON) = 0.035 Ω @ VGS = -4.5 V
±• Extended VGSS range ( 25V) for battery applications.
• Low gate charge (19nC typical).
• Fast switching speed.
• High performance trench technology for extremely
low RDS(ON).
• High power and current handling capability.
D
D
D
D
5
6
SO-8
G
SS
S
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol
Parameter
VDSS
VGSS
ID
PD
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Power Dissipation for Single Operation
(Note 1a)
(Note 1a)
(Note 1b)
(Note 1c)
TJ, Tstg
Operating and Storage Junction Temperature Range
7
8
4
3
2
1
Ratings
-30
±25
-8.8
-50
2.5
1.2
1
-55 to +150
Units
V
V
A
W
°C
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
RθJC Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
50
25
°C/W
°C/W
Package Outlines and Ordering Information
Device Marking
Device
Reel Size
FDS6685
FDS6685
13’’
Tape Width
12mm
Quantity
2500 units
1999 Fairchild Semiconductor Corporation
FDS6685 Rev. B
1 Page Typical Characteristics
50
VGS = -10V
40 -7.0V
-6.0V
-5.0V
-4.5V
30
20
-4.0V
10 -3.5V
0
012345
-VDS, DRAIN-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
1.6
ID = -8.8A
VGS = -10V
1.4
1.2
1
0.8
0.6
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. On-Resistance Variation
with Temperature
50
VDS = -5V
40
TA = -55oC
25oC
125oC
30
20
10
0
12345
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
6
2.6
2.4
2.2 VGS = -4.0V
2
1.8 -4.5V
1.6 -5.0V
1.4 -6.0V
1.2 -7.0V
-8.0V
1 -10V
0.8
0
10 20 30 40
-ID, DIRAIN CURRENT (A)
50
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage
0.06
0.05
0.04
0.03
0.02
0.01
0
3
ID = -4.4A
TA = 125oC
TA = 25oC
456789
-VGS, GATE TO SOURCE VOLTAGE (V)
10
Figure 4. On-Resistance Variation
with Gate-to-Source Voltage
100
VGS = 0V
10
1 TA = 125oC
0.1
0.01
25oC
-55oC
0.001
0.0001
0
0.2 0.4 0.6 0.8 1 1.2
-VSD, BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature
FDS6685 Rev. B
3Pages SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0
T
P0
D0
K0
Wc
B0
Tc
A0 P1 D1
User Direction of Feed
E1
F
E2
W
Dimensions are in millimeter
Pkg type
A0
SOIC(8lds) 6.50
(12mm)
+/-0.10
B0
5.30
+/-0.10
W
12.0
+/-0.3
D0 D1 E1 E2
1.55
+/-0.05
1.60
+/-0.10
1.75
+/-0.10
10.25
min
F P1
5.50
+/-0.05
8.0
+/-0.1
P0
4.0
+/-0.1
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum
Typical
component
cavity
B0 center line
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
SOIC(8lds) Reel Configuration: Figure 4.0
Typical
component
A0 center line
Sketch B (Top View)
Component Rotation
K0
2.1
+/-0.10
T
0.450
+/-
0.150
Wc
9.2
+/-0.3
Tc
0.06
+/-0.02
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
W1 Measured at Hub
Dim A
Max
Dim A
max
Dim N
See detail AA
7" Diameter Option
B Min
Dim C
See detail AA
Dim D
W3 min
13" Diameter Option
W2 max Measured at Hub
Tape Size
Reel
Option
12mm
7" Dia
12mm
13" Dia
Dimensions are in inches and millimeters
Dim A Dim B
Dim C
7.00
177.8
13.00
330
0.059
1.5
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
512 +0.020/-0.008
13 +0.5/-0.2
Dim D
0.795
20.2
0.795
20.2
Dim N
2.165
55
7.00
178
Dim W1
0.488 +0.078/-0.000
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
DETAIL AA
Dim W2
0.724
18.4
0.724
18.4
Dim W3 (LSL-USL)
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
© 1998 Fairchild Semiconductor Corporation
July 1999, Rev. B
6 Page | |||
ページ | 合計 : 8 ページ | ||
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