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FDS6680A の電気的特性と機能

FDS6680AのメーカーはFairchild Semiconductorです、この部品の機能は「Single N-Channel/ Logic Level/ PowerTrenchTM MOSFET」です。


製品の詳細 ( Datasheet PDF )

部品番号 FDS6680A
部品説明 Single N-Channel/ Logic Level/ PowerTrenchTM MOSFET
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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FDS6680A Datasheet, FDS6680A PDF,ピン配置, 機能
June 1998
FDS6680A
Single N-Channel, Logic Level, PowerTrenchTM MOSFET
GeneralDescription
This N-Channel Logic Level MOSFET is produced
using Fairchild Semiconductor's advanced PowerTrench
process that has been especially tailored to minimize
the on-state resistance and yet maintain superior
switching performance.
These devices are well suited for low voltage and battery
powered applications where low in-line power loss and
fast switching are required.
Features
12.5 A, 30 V. RDS(ON) = 0.0095 @ VGS = 10 V
RDS(ON) = 0.013 @ VGS = 4.5 V.
Fast switching speed.
Low gate charge.
High performance trench technology for
extremely low RDS(ON).
High power and current handling capability.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
D
D
D
D
F6D6S80A
SO-8
pin 1
S
G
S
S
5
6
7
8
Absolute Maximum Ratings
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current - Continuous
- Pulsed
TA = 25oC unless other wise noted
(Note 1a)
PD Power Dissipation for Single Operation (Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
FDS6680A
30
±20
12.5
50
2.5
1.2
1
-55 to 150
50
25
SOIC-16
4
3
2
1
Units
V
V
A
W
°C
°C/W
°C/W
FDS6680A Rev.D1

1 Page





FDS6680A pdf, ピン配列
Typical Electrical Characteristics
50
VGS = 10V 4.5V
40 6.0V
4.0V
3.5V
30
20
3.0V
10
2.5V
0
0 0.5 1 1.5
VDS , DRAIN-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics.
2
1.8
ID = 12.5A
1.6 V GS = 10V
1.4
1.2
1
0.8
0.6
-50
-25
0 25 50 75 100 125 150
TJ , JUNCTION TEMPERATURE (°C)
Figure 3. On-Resistance Variation with
Temperature.
50
VDS =5.0V
40
30
TJ = -55°C
25°C
125°C
20
10
0
1234
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5 . Transfer Characteristics.
3
V GS= 3.0V
2.5
2
3.5 V
4.0 V
1.5 4.5 V
5.5V
7.0V
1 10V
0 10 20 30 40 50
ID , DRAIN CURRENT (A)
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.04
I D = 6.3A
0.03
0.02
0.01
0
2
125°C
25°C
468
VGS , GATE TO SOURCE VOLTAGE (V)
10
Figure 4 . On Resistance Variation with
Gate-to-Source Voltage.
40
10 VGS= 0V
1
0.1
TJ = 125°C
25°C
-55°C
0.01
0.001
0.0001
0
0.2 0.4 0.6 0.8
1
VSD , BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 6 . Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDS6680A Rev.D1


3Pages


FDS6680A 電子部品, 半導体
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0
T
P0
D0
K0
Wc
B0
Tc
A0 P1 D1
User Direction of Feed
E1
F
E2
W
Dimensions are in millimeter
Pkg type
A0
SOIC(8lds) 6.50
(12mm)
+/-0.10
B0
5.30
+/-0.10
W
12.0
+/-0.3
D0 D1 E1 E2
1.55
+/-0.05
1.60
+/-0.10
1.75
+/-0.10
10.25
min
F P1
5.50
+/-0.05
8.0
+/-0.1
P0
4.0
+/-0.1
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum
Typical
component
cavity
B0 center line
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
SOIC(8lds) Reel Configuration: Figure 4.0
Typical
component
A0 center line
Sketch B (Top View)
Component Rotation
K0
2.1
+/-0.10
T
0.450
+/-
0.150
Wc
9.2
+/-0.3
Tc
0.06
+/-0.02
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
W1 Measured at Hub
Dim A
Max
Dim A
max
Dim N
See detail AA
7" Diameter Option
B Min
Dim C
See detail AA
Dim D
W3 min
13" Diameter Option
W2 max Measured at Hub
Tape Size
Reel
Option
12mm
7" Dia
12mm
13" Dia
Dimensions are in inches and millimeters
Dim A Dim B
Dim C
7.00
177.8
13.00
330
0.059
1.5
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
512 +0.020/-0.008
13 +0.5/-0.2
Dim D
0.795
20.2
0.795
20.2
Dim N
2.165
55
7.00
178
Dim W1
0.488 +0.078/-0.000
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
DETAIL AA
Dim W2
0.724
18.4
0.724
18.4
Dim W3 (LSL-USL)
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
© 1998 Fairchild Semiconductor Corporation
July 1999, Rev. B

6 Page



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共有リンク

Link :


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