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FDS6680のメーカーはFairchild Semiconductorです、この部品の機能は「Single N-Channel Logic Level PWM Optimized PowerTrenchTM MOSFET」です。 |
部品番号 | FDS6680 |
| |
部品説明 | Single N-Channel Logic Level PWM Optimized PowerTrenchTM MOSFET | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとFDS6680ダウンロード(pdfファイル)リンクがあります。 Total 8 pages
April 1998
FDS6680
Single N-Channel Logic Level PWM Optimized PowerTrenchTM MOSFET
General Description
This N-Channel Logic Level MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers.
The MOSFET features faster switching and lower gate
charge than other MOSFETs with comparable RDS(ON)
specifications.
The result is a MOSFET that is easy and safer to drive (even
at very high frequencies), and DC/DC power supply designs
with higher overall efficiency.
Features
11.5 A, 30 V. RDS(ON) = 0.010 Ω @ VGS = 10 V
RDS(ON) = 0.015 Ω @ VGS = 4.5 V.
Optimized for use in switching DC/DC converters with
PWM controllers.
Very fast switching.
Low gate charge (typical Qg = 19 nC).
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
54
63
72
81
Absolute Maximum Ratings
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current - Continuous
- Pulsed
TA = 25oC unless other wise noted
(Note 1a)
PD Power Dissipation for Single Operation (Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
FDS6680
30
±20
11.5
50
2.5
1.2
1
-55 to 150
50
25
Units
V
V
A
W
°C
°C/W
°C/W
FDS6680 Rev.E1
1 Page Typical Electrical Characteristics
50
VGS= 10V
6.0
40 5.0
4.5
4.0
30
20
3.5
10
3.0
0
0 0.5 1 1.5 2
VDS , DRAIN-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics.
2.5
1.8
ID = 11.5A
1.6 VGS =10V
1.4
1.2
1
0.8
0.6
-50
-25
0 25 50 75 100 125 150
TJ , JUNCTION TEMPERATURE (°C)
Figure 3. On-Resistance Variation with
Temperature.
50
VDS = 10V
40
TJ = -55°C
25°C
125°C
30
20
10
0
012345
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
3
2.5 VGS = 3.5V
2 4.0
4.5
1.5 5.0
6.0
1 10
0.5
0
10 20 30 40
I D , DRAIN CURRENT (A)
50
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.04
ID = 11.5A
0.03
0.02
0.01
0
2
TA = 125 oC
TA = 25 oC
468
VGS ,GATE-SOURCE VOLTAGE (V)
10
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
50
VGS =0V
10
1
0.1
0.01
TJ = 125°C
25°C
-55°C
0.001
0.0001
0.2
0.4 0.6 0.8
1
VSD , BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDS6680 Rev.E1
3Pages SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0
T
P0
D0
K0
Wc
B0
Tc
A0 P1 D1
User Direction of Feed
E1
F
E2
W
Dimensions are in millimeter
Pkg type
A0
SOIC(8lds) 6.50
(12mm)
+/-0.10
B0
5.30
+/-0.10
W
12.0
+/-0.3
D0 D1 E1 E2
1.55
+/-0.05
1.60
+/-0.10
1.75
+/-0.10
10.25
min
F P1
5.50
+/-0.05
8.0
+/-0.1
P0
4.0
+/-0.1
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum
Typical
component
cavity
B0 center line
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
SOIC(8lds) Reel Configuration: Figure 4.0
Typical
component
A0 center line
Sketch B (Top View)
Component Rotation
K0
2.1
+/-0.10
T
0.450
+/-
0.150
Wc
9.2
+/-0.3
Tc
0.06
+/-0.02
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
W1 Measured at Hub
Dim A
Max
Dim A
max
Dim N
See detail AA
7" Diameter Option
B Min
Dim C
See detail AA
Dim D
W3 min
13" Diameter Option
W2 max Measured at Hub
Tape Size
Reel
Option
12mm
7" Dia
12mm
13" Dia
Dimensions are in inches and millimeters
Dim A Dim B
Dim C
7.00
177.8
13.00
330
0.059
1.5
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
512 +0.020/-0.008
13 +0.5/-0.2
Dim D
0.795
20.2
0.795
20.2
Dim N
2.165
55
7.00
178
Dim W1
0.488 +0.078/-0.000
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
DETAIL AA
Dim W2
0.724
18.4
0.724
18.4
Dim W3 (LSL-USL)
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
© 1998 Fairchild Semiconductor Corporation
July 1999, Rev. B
6 Page | |||
ページ | 合計 : 8 ページ | ||
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部品番号 | 部品説明 | メーカ |
FDS6680 | Single N-Channel Logic Level PWM Optimized PowerTrenchTM MOSFET | Fairchild Semiconductor |
FDS6680A | Single N-Channel/ Logic Level/ PowerTrenchTM MOSFET | Fairchild Semiconductor |
FDS6680AS | 30V N-Channel PowerTrench SyncFET | Fairchild Semiconductor |
FDS6680S | 30V N-Channel PowerTrench SyncFET | Fairchild Semiconductor |