|
|
FDC6324のメーカーはFairchild Semiconductorです、この部品の機能は「Integrated Load Switch」です。 |
部品番号 | FDC6324 |
| |
部品説明 | Integrated Load Switch | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとFDC6324ダウンロード(pdfファイル)リンクがあります。 Total 10 pages
March 1999
FDC6324L
Integrated Load Switch
General Description
These Integrated Load Switches are produced using
Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is
especially tailored to minimize on-state resistance and
provide superior switching performance. These devices
are particularly suited for low voltage high side load
switch application where low conduction loss and ease
of driving are needed.
Features
VDROP=0.2V @ VIN=12V, IL=1A, VON/OFF=1.5 to 8V
VDROP=0.3V @ VIN=5V, IL=1A, VON/OFF=1.5 to 8V.
High density cell design for extremely low on-resistance.
VON/OFF Zener protection for ESD ruggedness.
>6KV Human Body Model.
SuperSOTTM-6 package design using copper lead frame for
superior thermal and electrical capabilities.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
pin 1
SuperSOT TM-6
Vin,R1 4
O N / O FF 5
R1,C1 6
Q2
Q1
3 Vout,C1
2 Vout,C1
IN
EQUIVALENT CIRCUIT
+VDROP -
1 R2
O N / O FF
OUT
See Application Circuit
Absolute Operating Range TA = 25°C unless otherwise noted
Symbol Parameter
VIN
VON/OFF
IL
Input Voltage Range
ON/OFF Voltage Range
Load Current @ VDROP=0.5V - Continuous
- Pulsed
(Note 1)
(Note 1 & 3)
PD
TJ,TSTG
ESD
Maximum Power Dissipation
(Note 2a)
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D Human Body
Model (100pf/1500Ohm)
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 2a)
RθJC Thermal Resistance, Junction-to-Case (Note 2)
FDC6324L
3 - 20
1.5 - 8
1.5
2.5
0.7
-55 to 150
6
180
60
Units
V
V
A
W
°C
kV
°C/W
°C/W
© 1999 Fairchild Semiconductor Corporation
FDC6324L Rev. D
1 Page Typical Electrical Characteristics (TA = 25 OC unless otherwise noted )
0.5
0.4
0.3
0.2
0.1
0
0
TJ = 125°C
TJ = 25°C
VIN = 12V
V ON/OFF = 1.5 - 8V
PW =300us, D≤ 2%
123
I L ,(A)
4
0.5
0.4
0.3
0.2
0.1
0
0
TJ = 125°C
TJ = 25°C
VIN = 5V
V ON/OFF = 1.5 - 8V
PW =300us, D≤ 2%
123
I L (A)
4
Figure 1. VDROP Versus IL at VIN=12V.
Figure 2. VDROP Versus IL at VIN=5.0V.
1
0.8
0.6
0.4
0.2
0
1
I L = 1A
VON/OFF = 1.5 - 8V
PW =300us, D≤ 2%
TJ = 125°C
TJ = 25°C
23
V IN (V)
4
5
Figure 3. VDROP Versus VIN at IL=1A.
1
0.8
0.6
0.4
0.2
0
1
I L = 1A
V ON/OFF = 1.5 - 8V
PW =300us, D≤ 2%
TJ = 125°C
TJ = 25°C
23
VIN , (V)
4
5
Figure 5. On Resistance Variation with
Input Voltage.
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0
TJ = 125°C
IL = 1A
VIN = 5V
PW =300us, D≤ 2%
TJ = 25°C
12345
IL , (A)
Figure 4. R(ON) Versus IL at VIN=5.0V.
FDC6324L Rev.D
3Pages FDC6324L Load Switch Application
APPLICATION CIRCUIT
Q2
IN
R1
C1
OUT
O N / O FF
Q1 Co LOAD
R2
General Description
This device is particularly suited for computer
peripheral switching applications where 20V
input and 1A output current capability are
needed. This load switch integrates a small
N-Channel Power MOSFET (Q1) which drives a
large P-Channel Power MOSFET (Q2) in one
tiny SuperSOTTM-6 package.
A load switch is usually configured for high side
switching so that the load can be isolated from
the active power source. A P-Channel Power
MOSFET, because it does not require its drive
voltage above the input voltage, is usually more
cost effective than using an N-Channel device in
this particular application. A large P-Channel
Power MOSFET minimizes voltage drop. By
using a small N-Channel device the driving
stage is simplified.
Component Values
R1 Typical 10k - 1MΩ
R2 Typical 0 - 10kΩ
C1 Typical 1000pF
(optional)
(optional)
Design Notes
R1 is needed to turn off Q2.
R2 can be used to soft start the switch in the case the output capacitance Co is small.
R2 ≤ should be at least 10 times smaller than R1 to guarantee Q1 turns on.
By using R1 and R2 a certain amount of current is lost from the input. This bias current loss is given by
the equation
=I BIAS_LOSS
Vin
R 1 +R2
when the switch is ON. IBIAS_LOSS can be minimized by large R1.
R2 and CRSS of Q2 make ramp for slow turn on. If excessive overshoot current occurs due to fast turn on,
additional capacitance C1 can be added externally to slow down the turn on.
FDC6324L Rev. D
6 Page | |||
ページ | 合計 : 10 ページ | ||
|
PDF ダウンロード | [ FDC6324 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
FDC6320 | Dual N & P Channel / Digital FET | Fairchild Semiconductor |
FDC6320C | Dual N & P Channel / Digital FET | Fairchild Semiconductor |
FDC6321C | Dual N & P Channel / Digital FET | Fairchild Semiconductor |
FDC6322 | Dual N & P Channel / Digital FET | Fairchild Semiconductor |