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FIN1019 の電気的特性と機能

FIN1019のメーカーはFairchild Semiconductorです、この部品の機能は「3.3V LVDS High Speed Differential Driver/Receiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 FIN1019
部品説明 3.3V LVDS High Speed Differential Driver/Receiver
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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FIN1019 Datasheet, FIN1019 PDF,ピン配置, 機能
April 2001
Revised September 2001
FIN1019
3.3V LVDS High Speed Differential Driver/Receiver
General Description
This driver and receiver pair are designed for high speed
interconnects utilizing Low Voltage Differential Signaling
(LVDS) technology. The driver translates LVTTL signals to
LVDS levels with a typical differential output swing of
350mV and the receiver translates LVDS signals, with a
typical differential input threshold of 100mV, into LVTTL
levels. LVDS technology provides low EMI at ultra low
power dissipation even at high frequencies. This device is
ideal for high speed clock or data transfer.
Features
s Greater than 400Mbs data rate
s 3.3V power supply operation
s 0.5ns maximum differential pulse skew
s 2.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s 100mV receiver input sensitivity
s Fail safe protection open-circuit, shorted and terminated
conditions
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Flow-through pinout simplifies PCB layout
s 14-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number Package Number
Package Description
FIN1019M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FIN1019MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
Connection Diagram
Inputs
Outputs
RIN+
L
RIN
H
RE
L
ROUT
L
H LL
H
X XH
Z
Fail Safe Condition
L
H
DIN
DE
DOUT+
DOUT
L H LH
H H HL
X L ZZ
OpenCircuit or Z
H
LH
H = HIGH Logic Level
Z = High Impedance
L = LOW Logic Level
X = Don’t Care
Fail Safe = Open, Shorted, Terminated
Pin Descriptions
Pin Name
DIN
DOUT+
DOUT
DE
RIN+
RIN
ROUT
RE
VCC
GND
NC
Description
LVTTL Data Input
Non-inverting LVDS Output
Inverting LVDS Output
Driver Enable (LVTTL, Active HIGH)
Non-Inverting LVDS Input
Inverting LVDS Input
LVTTL Receiver Output
Receiver Enable (LVTTL, Active LOW)
Power Supply
Ground
No Connect
© 2001 Fairchild Semiconductor Corporation DS500506
www.fairchildsemi.com

1 Page





FIN1019 pdf, ピン配列
DC Electrical Characteristics (Continued)
Device Characteristics
ICC Power Supply Current
Driver Enabled, Driver Load: RL = 100
Receiver Disabled, No Receiver Load
Driver Enabled, Driver Load: RL = 100 ,
Receiver Enabled, (RIN+ = 1V and RIN= 1.4V)
or (RIN+ = 1.4V and ROUT= 1V)
Driver Disabled, Receiver Enabled,
(RIN+ = 1V and RIN= 1.4V) or
(RIN+ = 1.4V and RIN= 1V)
Driver Disabled, Receiver Disabled
CIN Input Capacitance
Any LVTTL or LVDS Input
COUT
Output Capacitance
Any LVTTL or LVDS Output
Note 2: All typical values are at TA = 25°C and with VCC = 3.3V.
12.5
mA
12.5
mA
7.0 mA
7.0 mA
4 pF
6 pF
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min Typ Max
(Note 3)
Units
Driver Timing Characteristics
tPLHD
Differential Propagation Delay
LOW-to-HIGH
0.5 1.5 ns
tPHLD
Differential Propagation Delay
HIGH-to-LOW
RL = 100 , CL = 10 pF,
tTLHD
Differential Output Rise Time (20% to 80%) See Figure 2 and Figure 3
tTHLD
Differential Output Fall Time (80% to 20%)
tSK(P)
Pulse Skew |tPLH - tPHL|
tSK(PP)
Part-to-Part Skew (Note 4)
tZHD Differential Output Enable Time from Z to HIGH RL = 100, CL = 10 pF,
tZLD Differential Output Enable Time from Z to LOW See Figure 4 and Figure 5
tHZD Differential Output Disable Time from HIGH to Z
tLZD Differential Output Disable Time from LOW to Z
Receiver Timing Characteristics
0.5
0.4
0.4
1.5 ns
1.0 ns
1.0 ns
0.5 ns
1.0 ns
5.0 ns
5.0 ns
5.0 ns
5.0 ns
tPLH Propagation Delay LOW-to-HIGH
0.9 2.5 ns
tPHL Propagation Delay HIGH-to-LOW
0.9 2.5 ns
tTLH Output Rise time (20% to 80%)
|VID| = 400 mV, CL = 10 pF,
0.5 ns
tTHL Output Fall time (80% to 20%)
See Figure 6 and Figure 7
0.5 ns
tSK(P)
Pulse Skew | tPLH - tPHL |
0.5 ns
tSK(PP)
Part-to-Part Skew (Note 4)
1.0 ns
tZH LVTTL Output Enable Time from Z to HIGH
5.0 ns
tZL
LVTTL Output Enable Time from Z to LOW
RL = 500 , CL = 10 pF,
5.0 ns
tHZ LVTTL Output Disable Time from HIGH to Z See Figure 8
5.0 ns
tLZ LVTTL Output Disable Time from LOW to Z
5.0 ns
Note 3: All typical values are at TA = 25°C and with VCC = 5V.
Note 4: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
3 www.fairchildsemi.com


3Pages


FIN1019 電子部品, 半導体
FIGURE 7. LVDS Input to LVTTL Output AC Waveforms
Test Circuit for LVTTL Outputs
Voltage Waveforms Enable and Disable Times
FIGURE 8. LVTTL Outputs Test Circuit and AC Waveforms
www.fairchildsemi.com
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