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PDF FGB30N6S2D Data sheet ( Hoja de datos )
| Número de pieza | FGB30N6S2D | |
| Descripción | 600V/ SMPS II Series N-Channel IGBT with Anti-Parallel StealthTM Diode | |
| Fabricantes | Fairchild Semiconductor | |
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July 2001
FGH30N6S2D / FGP30N6S2D / FGB30N6S2D
600V, SMPS II Series N-Channel IGBT with Anti-Parallel StealthTM Diode
General Description
The FGH30N6S2D, FGP30N6S2D, and FGB30N6S2D are
Low Gate Charge, Low Plateau Voltage SMPS II IGBTs
combining the fast switching speed of the SMPS IGBTs
along with lower gate charge and plateau voltage and ava-
lanche capability (UIS). These LGC devices shorten delay
times, and reduce the power requirement of the gate drive.
These devices are ideally suited for high voltage switched
mode power supply applications where low conduction
loss, fast switching times and UIS capability are essential.
SMPS II LGC devices have been specially designed for:
• Power Factor Correction (PFC) circuits
• Full bridge topologies
• Half bridge topologies
• Push-Pull circuits
• Uninterruptible power supplies
• Zero voltage and zero current switching circuits
IGBT formerly Developmental Type TA49336
Diode formerly Developmental Type TA49390
Features
• 100kHz Operation at 390V, 14A
• 200kHZ Operation at 390V, 9A
• 600V Switching SOA Capability
• Typical Fall Time. . . . . . . . . . . 90ns at TJ = 125oC
• Low Gate Charge . . . . . . . . . 23nC at VGE = 15V
• Low Plateau Voltage . . . . . . . . . . . . .6.5V Typical
• UIS Rated . . . . . . . . . . . . . . . . . . . . . . . . . 150mJ
• Low Conduction Loss
Package
JEDEC STYLE TO-247
Symbol
E
C
JEDEC STYLE TO-220AB
G EC G
JEDEC STYLE TO-263AB
CG
C
G
E
E
Device Maximum Ratings TC= 25°C unless otherwise noted
Symbol
Parameter
Ratings
Units
BVCES Collector to Emitter Breakdown Voltage
600 V
IC25 Collector Current Continuous, TC = 25°C
45 A
IC110
Collector Current Continuous, TC = 110°C
20 A
ICM Collector Current Pulsed (Note 1)
108 A
VGES
Gate to Emitter Voltage Continuous
±20 V
VGEM Gate to Emitter Voltage Pulsed
±30 V
SSOA Switching Safe Operating Area at TJ = 150°C, Figure 2
60A at 600V
EAS Pulsed Avalanche Energy, ICE = 12A, L = 2mH, VDD = 50V
150 mJ
PD Power Dissipation Total TC = 25°C
167 W
Power Dissipation Derating TC > 25°C
1.33
W/°C
TJ Operating Junction Temperature Range
-55 to 150
°C
TSTG
Storage Junction Temperature Range
-55 to 150
°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. Pulse width limited by maximum junction temperature.
©2001 Fairchild Semiconductor Corporation
FGH30N6S2D / FGP30N6S2D / FGB30NS2D Rev. A
1 page  
Typical Performance Curves (Continued)
175
DUTY CYCLE < 0.5%, VCE = 10V
150 PULSE DURATION = 250µs
125
TJ = 25oC
100
75
50
25 TJ = 125oC
TJ = -55oC
0
5 6 7 8 9 10 11 12 13 14 15
VGE , GATE TO EMITTER VOLTAGE (V)
Figure 13. Transfer Characteristic
16
16
IG(REF) = 1mA, RL = 25Ω, TJ = 25oC
14
12
VCE = 600V
10
8
6
VCE = 400V
4
VCE = 200V
2
0 0 2 4 6 8 10 12 14 16 18 20 22 24
QG, GATE CHARGE (nC)
Figure 14. Gate Charge
1.2
RG = 10Ω, L = 500mH, VCE = 390V, VGE = 15V
1.0 ETOTAL = EON2 + EOFF
0.8
ICE = 24A
0.6
0.4 ICE = 12A
0.2
ICE = 6A
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
Figure 15. Total Switching Loss vs Case
Temperature
10
TJ = 125oC, L = 500µH, VCE = 390V, VGE = 15V
ETOTAL = EON2 + EOFF
ICE = 24A
1
ICE = 12A
ICE = 6A
0.1
1.0
10 100
RG, GATE RESISTANCE (Ω)
1000
Figure 16. Total Switching Loss vs Gate
Resistance
1.4
FREQUENCY = 1MHz
1.2
1.0
0.8
CIES
0.6
0.4
COES
0.2
0.0
0
CRES
10 20 30 40 50 60 70 80
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
90 100
Figure 17. Capacitance vs Collector to Emitter
Voltage
3.5
DUTY CYCLE < 0.5%
PULSE DURATION = 250µs, TJ = 25oC
3.0
2.5 ICE = 24A
ICE = 12A
2.0
ICE = 6A
1.5
6 7 8 9 10 11 12 13 14 15 16
VGE, GATE TO EMITTER VOLTAGE (V)
Figure 18. Collector to Emitter On-State Voltage vs
Gate to Emitter Voltage
©2001 Fairchild Semiconductor Corporation
FGH30N6S2D / FGP30N6S2D / FGB30NS2D Rev. A
5 Page 
TO-263AB SURFACE MOUNT JEDEC TO-263AB PLASTIC PACKAGE
H1
D
E
L
1
b
TERM. 4
3
e
e1
L2
b1
A
A1
TERM. 4
L1
J1
0.450
(11.43)
c
b2
31
L3
0.700
(17.78)
0.350
(8.89)
0.150
(3.81)
0.080 TYP (2.03)
0.062 TYP (1.58)
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.170 0.180 4.32 4.57
-
A1 0.048 0.052 1.22 1.32 4, 5
b 0.030 0.034 0.77 0.86 4, 5
b1 0.045 0.055 1.15 1.39 4, 5
b2
0.310
-
7.88 -
2
c 0.018 0.022 0.46 0.55 4, 5
D
0.405 0.425 10.29 10.79
-
E
0.395 0.405 10.04 10.28
-
e
0.100 TYP
2.54 TYP
7
e1
0.200 BSC
5.08 BSC
7
H1
0.045 0.055 1.15 1.39
-
J1
0.095 0.105 2.42 2.66
-
L
0.175 0.195 4.45 4.95
-
L1 0.090 0.110 2.29 2.79 4, 6
L2
0.050 0.070 1.27 1.77
3
L3
0.315
-
8.01 -
2
NOTES:
1. These dimensions are within allowable dimensions of Rev.
C of JEDEC TO-263AB outline dated 2-92.
2. L3 and b2 dimensions established a minimum mounting
surface for terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L1 is the terminal length for soldering.
7. Position of lead to be measured 0.120 inches (3.05mm) from
bottom of dimension D.
8. Controlling dimension: Inch.
9. Revision 10 dated 5-99.
TO263AB
24mm TAPE AND REEL
1.5mm
DIA. HOLE
24mm
4.0mm
USER DIRECTION OF FEED
2.0mm
1.75mm
CL
©2001 Fairchild Semiconductor Corporation
COVER TAPE
16mm
GENERAL INFORMATION
1. 800 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
40mm MIN.
ACCESS HOLE
30.4mm
330mm
13mm
100mm
24.4mm
FGH30N6S2D / FGP30N6S2D / FGB30NS2D Rev. A
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet FGB30N6S2D.PDF ] | |
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