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M11B416256A-30T の電気的特性と機能

M11B416256A-30TのメーカーはETCです、この部品の機能は「256 K x 16 DRAM EDO PAGE MODE」です。


製品の詳細 ( Datasheet PDF )

部品番号 M11B416256A-30T
部品説明 256 K x 16 DRAM EDO PAGE MODE
メーカ ETC
ロゴ ETC ロゴ 




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M11B416256A-30T Datasheet, M11B416256A-30T PDF,ピン配置, 機能
EliteMT
DRAM
M11B416256A
256 K x 16 DRAM
EDO PAGE MODE
FEATURES
X16 organization
EDO (Extended Data-Output) access mode
2 CAS Byte/Word Read/Write operation
Single 5V ( ± 10%) power supply
TTL-compatible inputs and outputs
512-cycle refresh in 8ms
Refresh modes : RAS only, CAS BEFORE RAS (CBR)
and HIDDEN
JEDEC standard pinout
Key AC Parameter
tRAC
tCAC
tRC
tPC
-25 25 8 43 10
-28 28 9 48 11
-30 30 9 55 12
-35 35 10 65 14
-40 40 11 75 16
ORDERING INFORMATION - PACKAGE
40-pin 400mil SOJ
44 / 40-pin 400mil TSOP (TypeII)
PRODUCT NO.
M11B416256A-25J
M11B416256A-28J
M11B416256A-30J
M11B416256A-35J
M11B416256A-40J
M11B416256A-25T
M11B416256A-28T
M11B416256A-30T
M11B416256A-35T
M11B416256A-40T
PACKING TYPE
SOJ
TSOPII
GENERAL DESCRIPTION
The M11B416256A is a randomly accessed solid state memory, organized as 262,144 x 16 bits device. It offers Extended
Data-Output , 5V( ± 10%) single power supply. Access time (-25,-28,-30,-35,-40) and package type (SOJ, TSOP II) are optional
features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh capabilities.
Two access modes are supported by this device : Byte access and Word access. Use only one of the two CAS and leave
the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used.
CASL transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH
transiting low will output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
TSOP (TypeII) Top View
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSS
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 VSS
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 N C
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSS
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 VSS
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 N C
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
Elite Memory Technology Inc
Publication Date : Feb. 2004
Revision : 1.9
1/15

1 Page





M11B416256A-30T pdf, ピン配列
EliteMT
M11B416256A
ABSOLUTE MAXIMUM RATINGS
Voltage on Any pin Relative to Vss … ……-1V to +7V
Operating Temperature, TA (ambient) ….0 °C to +70 °C
Storage Temperature (plastic) ……….-55 °C to +150 °C
Power Dissipation …………………………………1.43W
Short Circuit Output Current ……………………50mA
Permanent device damage may occur if “Absolute
Maximum Ratings” are exceeded. This is a stress rating
only, and functional operation of the device above those
conditions indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS (0 °C TA 70 °C ; VCC = 5V ± 10% unless otherwise noted)
PARAMETER
CONDITIONS
SYMBOL MIN MAX UNITS NOTES
Supply Voltage
Supply Voltage
VCC 4.5 5.5 V 1
VSS 0 0 V
Input High Voltage
VIH 2.4 VCC +0.3 V
1
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
0V VIN VIH (max)
0V VOUT VCC
Output(s) disable
IOH = -5 mA
VIL -0.3 0.8 V 1
ILI -10 10 µ A
ILO -10 10 µ A
VOH 2.4
-
V
Output Low Voltage
IOL = 4.2 mA
VOL - 0.4 V
Note : 1.All Voltages referenced to VSS
PARAMETER
Operating Current
CONDITIONS
RAS , CAS cycling , tRC =min
MAX
UNITS NOTES
SYMBOL
-25 -28 -30 -35 -40
ICC1 210 190 170 150 135 mA 1,2
Standby Current
TTL interface , RAS , CAS = VIH ,
DOUT =High-Z
4 4 4 4 4 mA
ICC2
CMOS interface, RAS , CAS VCC-0.2V
2 2 2 2 2 mA
RAS only refresh Current tRC = min
ICC3 210 190 170 150 135 mA
EDO Page Mode Current tPC = min
ICC4 210 190 170 150 135 mA
Standby Current
RAS =VIH, CAS = VIL
ICC5 5 5 5 5 5 mA
CAS Before RAS
Refresh
Current
tRC = min
ICC6 210 190 170 150 135 mA
2
1,3
1
Note : 1. ICC max is specified at the output open condition.
2. Address can be changed twice or less while RAS =VIL .
3. Address can be changed once or less while CAS =VIH .
Elite Memory Technology Inc
Publication Date : Feb. 2004
Revision : 1.9
3/15


3Pages


M11B416256A-30T 電子部品, 半導体
EliteMT
M11B416256A
Notes :
1. Enables on-chip refresh and address counters.
2. VIH(min) and VIL(max) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL.
3. In addition to meet the transition rate specification,
all input signals must transit between VIH and VIL in a
monotonic manner.
4. Assume that tRCD < tRCD(max). If tRCD is greater than
the maximum recommended value shown in this
table, tRAC will increase by the amount that tRCD
exceeds the value shown.
5. Assume that tRCD tRCD (max)
6. If CAS is low at the falling edge of RAS , data-out
will be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS and
RAS must be pulsed high.
7. Operation within the tRCD limit ensures that tRCD
(max) can be met, tRCD (max) is specified as a
reference point only ; if tRCD is greater than the
specified tRCD (max) limit, access time is controlled
by tCAC.
8. Operation within the tRAD limit ensures that tRAD(max)
can be met. tRAD(max) is specified as a reference
point only ; if tRAD is greater than the specified tRAD
(max) limit, access time is controlled by tAA.
9. Either tRCH or tRRH must be satisfied for a READ
cycle.
10. tOFF1(max) defines the time at which the output
achieves the open circuit condition ; it is not a
reference to VOH or VOL.
11. tWCS, tRWD, tAWD and tCWD are restrictive operating
parameters in LATE WRITE and
READ-MODIFY-WRITE cycle only. If tWCS
tWCS(min) , the cycle is an EARLY WRITE cycle and
the data output will remain an open circuit throughout
the entire cycle. If tRWD tRWD(min) , tAWD tAWD(min)
and tCWD tCWD(min) , the cycle is READ-WRITE and
the data output will contain data read from the
selected cell. If neither of the above conditions is
met, the state of I/O (at access time and until CAS
and RAS or OE go
back to VIH ) is indeterminate. OE held high and
WE taken low after CAS goes low result in a LATE
WRITE ( OE -controlled) cycle.
12. Those parameters are referenced to CAS leading
edge in EARLY WRITE cycles and WE leading edge
in LATE WRITE or READ-MODIFY- WRITE cycles.
13. During a READ cycle, if OE is low then taken HIGH
before CAS goes high, I/O goes open, if OE is tied
permanently low, a LATE WRITE or
READ-MODIFY-WRITE operation is not possible.
14. An initial pause of 200µs is required after power-up
followed by eight RAS refresh cycles ( RAS only or
CBR) before proper device operation is assured. The
eight RAS cycle wake-ups should be repeated any
time the tREF refresh requirement is exceeded.
15. WRITE command is defined as WE going low.
16. LATE WRITE and READ-MODIFY-WRITE cycles must
have both tOFF2 and tOEH met ( OE high during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycles.
17. The I/Os open during READ cycles once tOFF1 or tOFF2
occur.
18. Referenced to the earlier CAS falling edge.
19. Referenced to the latter CAS rising edge.
20. Output parameter (I/O) is referenced to corresponding
CAS input, IO0~7 by CASL and IO8~15 by
CASH .
21. Last falling CAS edge to first rising CAS edge.
22. Last rising CAS edge to next cycle’s last rising
CAS edge.
23. Last rising CAS edge to first falling CAS edge.
24. Each CAS must meet minimum pulse width.
25. Referenced to the latter CAS falling edge.
26. All IOs controlled by OE , regardless CASL and
CASH .
Elite Memory Technology Inc
Publication Date : Feb. 2004
Revision : 1.9
6/15

6 Page



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部品番号部品説明メーカ
M11B416256A-30J

256 K x 16 DRAM EDO PAGE MODE

ETC
ETC
M11B416256A-30T

256 K x 16 DRAM EDO PAGE MODE

ETC
ETC


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