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M1040-11I156.2500 の電気的特性と機能

M1040-11I156.2500のメーカーはIntegrated Circuit Systemsです、この部品の機能は「VCSO BASED CLOCK PLL WITH AUTOSWITCH」です。


製品の詳細 ( Datasheet PDF )

部品番号 M1040-11I156.2500
部品説明 VCSO BASED CLOCK PLL WITH AUTOSWITCH
メーカ Integrated Circuit Systems
ロゴ Integrated Circuit Systems ロゴ 




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M1040-11I156.2500 Datasheet, M1040-11I156.2500 PDF,ピン配置, 機能
Integrated
Circuit
Systems, Inc.
Preliminary Information
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
The M1040 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock protection,
frequency translation and jitter
attenuation in OC-12/48 class optical
networking systems. It features dual
differential inputs with two modes of
input selection: manual and
automatic upon clock failure. The clock multiplication
ratios and output divider ratio are pin selectable. This
device provides two outputs. External loop components
allow the tailoring of PLL loop response.
FEATURES
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to
20MHz)
Output frequencies of 62.5 to 175 MHz *; Two differen-
tial LVPECL outputs (CML, LVDS options available)
Loss of Lock (LOL) indicator output
Narrow Bandwidth control input (NBW pin);
Initialization (INIT) input overrides NBW at power-up
Dual reference clock inputs support LVDS, LVPECL,
LVCMOS, LVTTL
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure; Hitless
Switching (HS), Phase Build-out (PBO) options enable
SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Industrial temperature available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
M1040
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
INIT
LOL
3
MR_SEL2:0
MUX
0
1
0
1
Auto
Ref Sel
R Div
LOL
Phase
Detector
M / R Divider
LUT
PLL
Phase
Detector
M Divider
PIN ASSIGNMENT (9 x 9 mm SMT)
MR_SEL1
MR_SEL0
REF_ACK
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30 16
31 M 1 0 4 0 15
32 14
33 ( T o p V i e w ) 13
34 12
35 11
36 10
P_SEL
INIT
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1040-11-155.5200
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
19.44
77.76
155.52
622.08
8 155.52
2 or
1 77.76
0.25
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
Loop Filter
VCSO
P Divider
(1 or 2)
FOUT0
nFOUT0
FOUT1
nFOUT1
P_SEL
Figure 2: Simplified Block Diagram
M1040 Datasheet Rev 0.1
Revised 11Nov2003
M1040 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400

1 Page





M1040-11I156.2500 pdf, ピン配列
Integrated
Circuit
Systems, Inc.
DETAILED BLOCK DIAGRAM
M1040
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
RLOOP CLOOP
OP_IN
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
RPOST
CPOST
CPOST
nOP_OUT nVC
VC
External
Loop Filter
Components
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
INIT
LOL
3
MR_SEL2:0
MUX
0
1
0
1
Auto
Ref Sel
R
Divider
PLL
Phase
Detector RIN
R IN
Loop Filter
Amplifier
LOL
Phase
Detector
M Divider
M / R Divider
LUT
P_SEL
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
P Divider
FOUT0
nFOUT0
FOUT1
nFOUT1
Figure 3: Detailed Block Diagram
PLL DIVIDER SELECTION TABLES
M and R Divider Look-Up Tables (LUT)
The MR_SEL2:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up is defined in
Table 3.
M1040 M/R Divider LUT
Total
MR_SEL3:0 M Div R Div PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
000
81
8
19.44
19.44
0 0 1 64 8
8
19.44
2.43
010
21
2
77.76
77.76
0 1 1 16 8
2
77.76
9.72
100
11
1
155.52
155.52
101
110
88
1
Test Mode1 N/A
155.52
N/A
19.44
N/A
111
2 8 0.25
622.08
77.76
Table 3: M1040 M/R Divider LUT
Note 1: Factory test mode; do not use.
Table 3 provides example Fin and phase detector
frequencies with 155.52MHz VCSO devices
(e.g., M1040-11-155.5200). See “Ordering Information”
on pg. 12.
General Guidelines for M and R Divider Selection
General guidelines for M/R divider selection (see
following pages for more detail):
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is 19.44MHz. The LOL pin should
not be used during loop timing mode.
When LOL is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make LOL
overly sensitive, and higher phase detector
frequencies make LOL less sensitive.
The preceding guideline also applies when using the
AutoSwitch Mode, since AutoSwitch uses the LOL
output for clock fault detection.
Post-PLL Divider
The M1040 also features a post-PLL (P) divider for the
output clocks. It divides the VCSO frequency to produce
one of two selectable output frequencies (1/2 or 1/1 of
the VCSO frequency). That selected frequency appears
on both clock output pairs. The P_SEL pin selects the
value for the P divider.
P_SEL
P Value
M1040-11-155.52
Output Frequency
(MHz)
1 2 77.76
0 1 155.52
Table 4: P Divider Selector Values and Frequencies
M1040 Datasheet Rev 0.1
3 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400


3Pages


M1040-11I156.2500 電子部品, 半導体
Integrated
Circuit
Systems, Inc.
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
AutoSwitch (AUTO) Reference Clock Reselection
This device offers an automatic reference clock
reselection feature for switching input reference clocks
upon a reference clock failure. With the AUTO input pin
set to high and the LOL output low, the device is placed
into automatic reselection (AutoSwitch) mode. Once in
AutoSwitch mode, when LOL then goes high (due to a
reference clock fault), the input clock reference is
automatically reselected internally, as indicated by the
state change of the REF_ACK output. Automatic clock
reselection is made only once (it is non-revertive).
Re-arming of automatic mode requires placing the
device into manual selection (Manual Select) mode
(AUTO pin low) before returning to AutoSwitch mode
(AUTO pin high).
Using the AutoSwitch Feature
See alsoTable 5, Example AutoSwitch Sequence.
In application, the system is powered up with the device
in Manual Select mode (AUTO pin is set low), allowing
sufficient time for the reference clock and device PLL to
settle. The REF_SEL input selects the reference clock to
be used in Manual Select mode and the initial reference
clock used in AutoSwitch mode. The REF_SEL input state
must be maintained when switching to AutoSwitch
mode (AUTO pin high) and must still be maintained until a
reference fault occurs.
Once a reference fault occurs, the LOL output goes high
and the input reference is automatically reselected. The
REF_ACK output always indicates the reference selection
status and the LOL output always indicates the PLL lock
status.
A successful automatic reselection is indicated by a
change of state of the REF_ACK output and a momentary
level high of the LOL output (minimum high time is 10
ns).
If an automatic reselection is made to a non-valid
reference clock (one to which the PLL cannot lock),
the REF_ACK output will change state but the LOL
output will remain high.
No further automatic reselection is made; only one
reselection is made each time the AutoSwitch mode is
armed. AutoSwitch mode is re-armed by placing the
device into Manual Select mode (AUTO pin low) and then
into AutoSwitch mode again (AUTO pin high).
Following an automatic reselection and prior to
selecting Manual Select mode (AUTO pin low), the
REF_SEL pin has no control of reference selection.
To prevent an unintential reference reselection,
AutoSwitch mode must not be re-enabled until the
desired state of the REF_SEL pin is set and the LOL output
is low. It is recommended to delay the re-arming of
AutoSwitch mode, following an automatic reselection,
to ensure the PLL is fully locked on the new reference.
In most system configurations, where loop bandwidth is
in the range of 100-1000 Hz and damping factor below
10, a delay of 500 ms should be sufficient. Until the PLL
is fully locked intermittent LOL pulses may occur.
Example AutoSwitch Sequence
0 = Low; 1 = High. Example with REF_SEL initially set to 0 (i.e., DIF_REF0 selected)
REF_SEL Selected REF_ACK AUTO LOL Conditions
Input Clock Input Output Input Output
Initialization
0 DIF_REF0 0
0 1 Device power-up. Manual Select mode. DIF_REF0 input selected reference, not yet locked to.
0 DIF_REF0 0
0 -0- LOL to 0: Device locked to reference (may get intermittent LOL pulses until fully locked).
0 DIF_REF0 0 -1- 0 AUTO set to 1: Device placed in AutoSwitch mode (with DIF_REF0 as initial reference clock).
Operation & Activation
0 DIF_REF0 0
1 0 Normal operation with AutoSwitch mode armed, with DIF_REF0 as initial reference clock.
0 DIF_REF0 0
0 -DIF_REF1- -1-
0 DIF_REF1 1
1 -1- LOL to 1: Clock fault on DIF_REF0, loss of lock indicated by LOL pin, ...
1 1 ... and immediate automatic reselection to DIF_REF1 (indicated by REF_ACK pin).
1 -0- LOL to 0: Device locks to DIF_REF1 (assuming valid clock on DIF_REF1).
-1- DIF_REF1 1
Re-initialization
1 0 REF_SEL set to 1: Prepares for Manual Selection of DIF_REF1 before then re-arming AutoSwitch.
1 DIF_REF1 1 -0- 0 AUTO set to 0: Manual Select mode entered briefly, manually selecting DIF_REF1 as reference.
1 DIF_REF1 1
-1- 0 AUTO set to 1: Device is placed in AutoSwitch mode (delay recommended to ensure device fully
locked), re-initializing AutoSwitch with DIF_REF1 now specified as the initial reference clock.
Table 5: Example AutoSwitch Sequence
M1040 Datasheet Rev 0.1
6 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400

6 Page



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部品番号部品説明メーカ
M1040-11I156.2500

VCSO BASED CLOCK PLL WITH AUTOSWITCH

Integrated Circuit Systems
Integrated Circuit Systems


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