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M-8880 の電気的特性と機能

M-8880のメーカーはClare Inc.です、この部品の機能は「M-8880 DTMF Transceiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 M-8880
部品説明 M-8880 DTMF Transceiver
メーカ Clare Inc.
ロゴ Clare  Inc. ロゴ 




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M-8880 Datasheet, M-8880 PDF,ピン配置, 機能
M-8880 DTMF Transceiver
· Advanced CMOS technology for low power consump-
tion and increased noise immunity
· Complete DTMF transmitter/receiver in a single chip
· Standard 6500/6800 series microprocessor port
· Central office quality and performance
· Adjustable guard time
· Automatic tone burst mode
· Call progress mode
· Single +5 Volt power supply
· 20-pin DIP and SOIC packages
· 2 MHz microprocessor port operation
· Inexpensive 3.58 MHz crystal
· No continuous f2 clock required, only strobe
· Applications include: paging systems, repeater sys-
tems/mobile radio, interconnect dialers, PBX systems,
computer systems, fax machines, pay telephones,
credit card verification
The M-8880 is a complete DTMF Transmitter/Receiver that fea-
tures adjustable guard time, automatic tone burst mode, call
progress mode, and a fully compatible 6500/6800 microproces-
sor interface. The receiver portion is based on the industry stan-
dard M-8870 DTMF Receiver, while the transmitter uses a
switched-capacitor digital-to-analog converter for
low-distortion, highly accurate DTMF signaling. Tone bursts can
be transmitted with precise timing by making use of the auto-
matic tone burst mode. To analyze call progress tones, a call
progress filter can be selected by an external microprocessor.
Figure 1 Pin Diagram
Functional Description
M-8880 functions consist of a high-performance DTMF receiver
with an internal gain setting amplifier and a DTMF generator that
contains a tone burst counter for generating precise tone bursts
and pauses. The call progress mode, when selected, allows the
detection of call progress tones. A standard 6500/6800 series
microprocessor interface allows access to an internal status
register, two control registers, and two data registers.
Input Configuration
The input arrangement consists of a differential input opera-
tional amplifier and bias sources (VREF) for biasing the amplifier
inputs at VDD/2. Provisions are made for the connection of a
feedback resistor to the op-amp output (GS) for gain adjust-
40-406-00012, Rev. G
Figure 2 Block Diagram
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M-8880 pdf, ピン配列
M-8880
causes VC (see Figure 5) to rise as the capacitor discharges.
Provided that the signal condition is maintained (ESt remains
high) for the validation period (tGTP), VC reaches the threshold
(VTSt) of the steering logic to register the tone pair, latching its
corresponding 4-bit code (see Table 2) into the receive data reg-
ister.
Table 2 Tone Encoding/Decoding
FLOW FHIGH Digit
D3
D2
D1
697 1209
1
0
0
0
697 1336
2
0
0
1
697 1477
3
0
0
1
770 1209
4
0
1
0
770 1336
5
0
1
0
770 1477
6
0
1
1
852 1209
7
0
1
1
852 1336
8
1
0
0
852 1477
9
1
0
0
941 1336
0
1
0
1
941 1209
*
1
0
1
941 1477
#
1
1
0
697 1633
A
1
1
0
770 1633
B
1
1
1
852 1633
C
1
1
1
941 1633
D
0
0
0
0 = logic low, 1 = logic high
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
At this point the StGT output is activated and drives VC to VDD.
StGT continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to settle, the
delayed steering output flag goes high, signaling that a received
tone pair has been registered. It is possible to monitor the status
of the delayed steering flag by checking the appropriate bit in the
status register. If interrupt mode has been selected, the IRQ/CP
pin will pull low when the delayed steering flag is active.
The steering circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate signal in-
terruptions (dropout) too short to be considered a valid pause.
This capability, together with the ability to select the steering
time constants externally, allows the designer to tailor perfor-
mance to meet a wide variety of system requirements.
Guard Time Adjustment: The simple steering circuit shown in
Figure 5 is adequate for most applications. Component values
are chosen according to the formula:
tREC = tDP + tGTP
TID = tDA + tGTA
The value of tDP is a device parameter and tREC is the minimum
signal duration to be recognized by the receiver. A value for C1
of 0.1 µF is recommended for most applications, leaving R1 to
be selected by the designer. Different steering arrangements
may be used to select independently the guard times for tone
present (tGTP) and tone absent (tGTA). This may be necessary to
meet system specifications that place both accept and reject
limits on both tone duration and interdigit pause. Guard time ad-
justment also allows the designer to tailor system parameters
such as talkoff and noise immunity. Increasing tREC improves
talkoff performance since it reduces the probability that tones
simulated by speech will maintain signal condition long enough
to be registered. Alternatively, a relatively short tREC with a long
tDO would be appropriate for extremely noisy environments
where fast acquisition time and immunity to tone dropouts are
required. Design information for guard time adjustment is shown
in Figure 6.
Figure 5 Basic Steering Circuit
The contents of the output latch are updated on an active de-
layed steering transition. This data is presented to the 4-bit
bidirectional data bus when the receive data register is read.
Figure 6 Guard Time Adjustment
Call Progress Filter
A call progress (CP) mode can be selected, allowing the detec-
tion of various tones that identify the progress of a telephone call
on the network. The call progress tone input and DTMF input are
common; however, call progress tones can only be detected
when the CP mode has been selected. DTMF signals cannot be
40-406-00012, Rev. G
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M-8880 電子部品, 半導体
M-8880
registers on powerup; however, as a precautionary measure the
initialization software should include a routine to clear the regis-
ters. Refer to Tables 3 and 4 for details on the control registers.
The IRQ/CP pin can be programmed to provide an interrupt re-
quest signal on validation of DTMF signals, or when the trans-
mitter is ready for more data (burst mode only). The IRQ/CP pin
is configured as an open-drain output device and as such re-
quires a pullup resistor (see Figure 10).
Ordering Information
M-888001P
M-8880-01SM
M-8880-01T
20-pin plastic DIP
20-pin plastic SOIC
20-pin plastic SOIC,Tape and Reel
Figure 9 Equations
Table 6 Internal Register Functions
RS0 R/W
Function
0 0 Write to transmitter
0 1 Read from receiver
1 0 Write to control register
1 1 Read from status register
b3
RSEL
Table 7 CRA Bit Postions
b2 b1
IRQ CP/DTMF
b0
TOUT
Table 8 CRB Bit Positions
b3 b2 b1 b0
C/R
S/D
TEST
BURST
Figure 10 Application Circuit (Single-Ended Input)
40-406-00012, Rev. G
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共有リンク

Link :


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