DataSheet.jp

M-8870-02T の電気的特性と機能

M-8870-02TのメーカーはClare Inc.です、この部品の機能は「DTMF Receiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 M-8870-02T
部品説明 DTMF Receiver
メーカ Clare Inc.
ロゴ Clare  Inc. ロゴ 




このページの下部にプレビューとM-8870-02Tダウンロード(pdfファイル)リンクがあります。
Total 9 pages

No Preview Available !

M-8870-02T Datasheet, M-8870-02T PDF,ピン配置, 機能
Features
Low Power Consumption
Adjustable Acquisition and Release Times
Central Office Quality and Performance
Power-down and Inhibit Modes (-02 only)
Inexpensive 3.58 MHz Time Base
Single 5 Volt Power Supply
Dial Tone Suppression
Applications
Telephone switch equipment
Remote data entry
Paging systems
Personal computers
Credit card systems
Pin Configuration
Block Diagram
M-8870
DTMF Receiver
Description
The M-8870 is a full DTMF Receiver that integrates
both bandsplit filter and decoder functions into a single
18-pin DIP or SOIC package. Manufactured using
CMOS process technology, the M-8870 offers low
power consumption (35 mW max) and precise data
handling. Its filter section uses switched capacitor
technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting
techniques to detect and decode all 16 DTMF tone
pairs into a 4-bit code. External component count is
minimized by provision of an on-chip differential input
amplifier, clock generator, and latched tri-state inter-
face bus. Minimal external components required
include a low-cost 3.579545 MHz color burst crystal, a
timing resistor, and a timing capacitor.
The M-8870-02 provides a “power-down” option
which, when enabled, drops consumption to less
than 0.5 mW. The M-8870-02 can also inhibit the
decoding of fourth column digits (see Tone Decoding
table on page 5).
Ordering Information
Part #
M-8870-01
Description
18-pin plastic DIP
M-8870-01SM 18-pin plastic SOIC
M-8870-01SMTR 18-pin plastic SOIC, tape and reel
M-8870-02
18-pin plastic DIP, power-down,
option
M-8870-02SM
18-pin plastic SOIC, power-down,
option
M-8870-02T
18-pin plastic SOIC, power-down
option, tape and reel
DS-M8870-R3
www.clare.com
1

1 Page





M-8870-02T pdf, ピン配列
M-8870
Functional Description
M-8870 operating functions (see block diagram on
page 1) include a bandsplit filter that separates the
high and low tones of the received pair, and a digital
decoder that verifies both the frequency and duration
of the received tones before passing the resulting 4-bit
code to the output bus.
Filter
The low and high group tones are separated by apply-
ing the dual-tone signal to the inputs of two 6th order
switched capacitor bandpass filters with bandwidths
that correspond to the bands enclosing the low and
high group tones. The filter also incorporates notches
at 350 and 440 Hz, providing excellent dial tone rejec-
tion. Each filter output is followed by a single-order
switched capacitor section that smooths the signals
prior to limiting. Signal limiting is performed by high-
gain comparators provided with hysteresis to prevent
detection of unwanted low-level signals and noise.
The comparator outputs provide full-rail logic swings
at the frequencies of the incoming tones.
Decoder
The M-8870 decoder uses a digital counting tech-
nique to determine the frequencies of the limited tones
and to verify that they correspond to standard DTMF
frequencies. A complex averaging algorithm is used to
protect against tone simulation by extraneous signals
(such as voice) while tolerating small frequency varia-
tions. The algorithm ensures an optimum combination
of immunity to talkoff and tolerance to interfering sig-
nals (third tones) and noise. When the detector rec-
ognizes the simultaneous presence of two valid tones
(known as signal condition), it raises the Early
Steering flag (ESt). Any subsequent loss of signal
condition will cause ESt to fall.
Basic Steering Circuit
Steering Circuit
Before a decoded tone pair is registered, the receiver
checks for a valid signal duration (referred to as char-
acter-recognition-condition). This check is performed
by an external RC time constant driven by ESt. A logic
high on ESt causes VC (see block diagram on page 1)
to rise as the capacitor discharges. Provided that sig-
nal condition is maintained (ESt remains high) for the
validation period (tGTF), VC reaches the threshold (VTSt)
of the steering logic to register the tone pair, thus latch-
ing its corresponding 4-bit code (see DC
Characteristics on page 2) into the output latch. At this
point, the GT output is activated and drives VC to VDD.
GT continues to drive high as long as ESt remains
high. Finally, after a short delay to allow the output
latch to settle, the delayed steering output flag (StD)
goes high, signaling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three-
state control input (OE) to a logic high. The steering
circuit works in reverse to validate the interdigit pause
between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate
signal interruptions (dropouts) too short to be consid-
ered a valid pause. This capability, together with the
ability to select the steering time constants externally,
allows the designer to tailor performance to meet a
wide variety of system requirements.
Single-Ended Input Configuration
Rev. 3 www.clare.com
3


3Pages


M-8870-02T 電子部品, 半導体
M-8870
AC Characteristics
Parameter
Symbol Min
Typ*
Max
Units
Valid input signal levels (each tone
- -29 - +1 dBm
of composite signal)
- 27.5 -
869 mVRMS
Positive twist accept
- - - 10
dB
Negative twist accept
- - - 10
dB
Frequency deviation accept limit
- - - ± 1.5% + 2 Hz Nom.
Frequency deviation reject limit
- ±3.5% - - Nom.
Third tone tolerance
- -25 -16
-
dB
Noise tolerance
- - -12 -
dB
Dial tone tolerance
- +18 +22
-
dB
Tone present detection time
tDP 5 8 14
ms
Tone absent detection time
tDA 0.5
3
8.5
ms
Minimum tone duration accept
tREC - - 40
ms
Maximum tone duration reject
tREC 20
-
-
ms
Minimum interdigit pause accept
tID - - 40
ms
Maximum interdigit pause reject
tDO 20
-
-
ms
Propagation delay (St to Q)
tPQ - 6 11
µs
Propagation delay (St to StD)
tPStD
-
9
16
µs
Output data setup (Q to StD)
tQStD - 4.0
-
µs
Propagation delay (OE to Q), enable
tPTE - 50 60
ns
Propagation delay (OE to Q), disable
tPTD - 300
-
ns
Crystal clock frequency
fCLK 3.5759 3.5795 3.5831
MHz
Clock output (OSC2), capacitive load CLO - - 30
pF
All voltages referenced to VSS unless otherwise noted. For typical values VDD = 5.0 V, VSS = 0 V, TA = 25°C, fCLK = 3.579545 MHz.
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Notes:
1. dBm = decibels above or below a reference power of 1 mW into a 600load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40 ms. Tone pause = 40 ms.
4. Nominal DTMF frequencies are used, measured at GS.
5. Both tones in the composite signal have an equal amplitude.
6. Bandwidth limited (0 to 3 kHz) Gaussian noise.
7. The precise dial tone frequencies are (350 and 440 Hz) ± 2%.
8. For an error rate of better than 1 in 10,000.
9. Referenced to lowest level frequency component in DTMF signal.
10. Minimum signal acceptance level is measured with specified maximum frequency deviation.
11. Input pins defined as IN+, IN-, and OE.
12. External voltage source used to bias VREF.
13. This parameter also applies to a third tone injected onto the power supply.
14. Referenced to Single - Ended Input Configuration on page 3. Input DTMF tone level at -28 dBm.
Notes
1,2,3,4,5,8
2,3,4,8
2,3,5,8,10
2,3,5
2,3,4,5,8,9,13,14
2,3,4,5,6,8,9
2,3,4,5,7,8,9
See Timing Diagram on page 7
User adjustable (see Basic Steering
Circuit and Guard Time Adjustment
on pages 3 and 4.)
OE = VDD
RL = 10 k, CL = 50 pF
-
-
6
www.clare.com
Rev. 3

6 Page



ページ 合計 : 9 ページ
 
PDF
ダウンロード
[ M-8870-02T データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
M-8870-02

DTMF Receiver

Clare  Inc.
Clare Inc.
M-8870-02SM

DTMF Receiver

Clare  Inc.
Clare Inc.
M-8870-02T

DTMF Receiver

Clare  Inc.
Clare Inc.


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap