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4069UB PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 4069UB
部品説明 Hex Inverter
メーカ Motorola Inc
ロゴ Motorola  Inc ロゴ 



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4069UB Datasheet, 4069UB PDF,ピン配置, 機能
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14068B
See Page 6-5
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure.
These inverters find primary use where low power dissipation and/or high
noise immunity is desired. Each of the six inverters is a single stage to
minimize propagation delays.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs (see Page 5–2)
Pin–for–Pin Replacement for CD4069UB
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMeets JEDEC UB Specifications
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVDD DC Supply Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout Input or Output Voltage (DC or Transient)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin, Iout Input or Output Current (DC or Transient),
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎper Pin
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
± 10
V
V
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation, per Package†
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature(8–SecondSoldering)
500
– 65 to + 150
260
mW
_C
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
LOGIC DIAGRAM
12
3
4
VDD = PIN 14
VSS = PIN 7
56
CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
VDD
INPUT*
OUTPUT
98
MC14069UB
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
IN 1
OUT 1
IN 2
OUT 2
IN 3
OUT 3
VSS
1
2
3
4
5
6
7
14 VDD
13 IN 6
12 OUT 6
11 IN 5
10 OUT 5
9 IN 4
8 OUT 4
11 10
13 12
VSS
* Double diode protection on all
inputs not shown.
PULSE
GENERATOR
INPUT
VDD
14
OUTPUT
7 VSS
CL
20 ns
INPUT
tPHL
OUTPUT
90%
50%
10%
90%
50%
10%
tTHL
Figure 1. Switching Time Test Circuit and Waveforms
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
20 ns
VDD
VSS
tPLH
VOH
VOL
tTLH
MC14069UB
1

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