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3D7501G PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 3D7501G
部品説明 MONOLITHIC MANCHESTER ENCODER
メーカ ETC
ロゴ ETC ロゴ 

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3D7501G Datasheet, 3D7501G PDF,ピン配置, 機能
MONOLITHIC MANCHESTER
ENCODER
(SERIES 3D7501)
3D7501
data
delay
3
®
devices, inc.
FEATURES
All-silicon, low-power CMOS
technology
TTL/CMOS compatible inputs and
outputs
Vapor phase, IR and wave
solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Maximum data rate: 50 MBaud
PACKAGES
CLK
RESB
DAT
GND
1
2
3
4
8 VDD
7 N/C
6 TXB
5 TX
3D7501M DIP (.300)
3D7501H Gull Wing (.300)
3D7501Z SOIC (.150)
CLK 1 14 VDD
N/C 2 13 N/C
N/C 3 12 N/C
RESB 4 11 N/C
DAT 5 10 N/C
N/C 6 9 TXB
GND 7 8 TX
3D7501 DIP (.300)
3D7501G Gull Wing (.300)
3D7501D SOIC (.150)
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7501 is a monolithic CMOS Manchester Encoder. The clock
and data, present at the unit input, are combined into a single bi-
phase-level signal. In this encoding mode, a logic one is represented
by a high-to-low transition within the bit cell, while a logic zero is
represented by a low-to-high transition. The unit operating baud rate (in
Mbaud) is equal to the input clock frequency (in MHZ) . All pins
marked N/C must be left unconnected.
DAT Data Input
CLK Clock Input
RESB Reset
TX Signal Output
TXB Inverted Signal Output
VCC +5 Volts
GND Ground
The all-CMOS 3D7501 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL Manchester Encoder. It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is
offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14-
pin SOICs.
Doc #96010
5/19/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
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