|
|
3D7501DのメーカーはETCです、この部品の機能は「MONOLITHIC MANCHESTER ENCODER」です。 |
部品番号 | 3D7501D |
| |
部品説明 | MONOLITHIC MANCHESTER ENCODER | ||
メーカ | ETC | ||
ロゴ | |||
このページの下部にプレビューと3D7501Dダウンロード(pdfファイル)リンクがあります。 Total 4 pages
MONOLITHIC MANCHESTER
ENCODER
(SERIES 3D7501)
3D7501
data
delay
3
®
devices, inc.
FEATURES
• All-silicon, low-power CMOS
technology
• TTL/CMOS compatible inputs and
outputs
• Vapor phase, IR and wave
solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Maximum data rate: 50 MBaud
PACKAGES
CLK
RESB
DAT
GND
1
2
3
4
8 VDD
7 N/C
6 TXB
5 TX
3D7501M DIP (.300)
3D7501H Gull Wing (.300)
3D7501Z SOIC (.150)
CLK 1 14 VDD
N/C 2 13 N/C
N/C 3 12 N/C
RESB 4 11 N/C
DAT 5 10 N/C
N/C 6 9 TXB
GND 7 8 TX
3D7501 DIP (.300)
3D7501G Gull Wing (.300)
3D7501D SOIC (.150)
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7501 is a monolithic CMOS Manchester Encoder. The clock
and data, present at the unit input, are combined into a single bi-
phase-level signal. In this encoding mode, a logic one is represented
by a high-to-low transition within the bit cell, while a logic zero is
represented by a low-to-high transition. The unit operating baud rate (in
Mbaud) is equal to the input clock frequency (in MHZ) . All pins
marked N/C must be left unconnected.
DAT Data Input
CLK Clock Input
RESB Reset
TX Signal Output
TXB Inverted Signal Output
VCC +5 Volts
GND Ground
The all-CMOS 3D7501 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL Manchester Encoder. It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads. It is
offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14-
pin SOICs.
Doc #96010
5/19/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1 Page 3D7501
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
VDD
VIN
IIN
TSTRG
-0.3 7.0
V
-0.3 VDD+0.3 V
-10 10 mA
-55 150 C
25C
Lead Temperature
TLEAD
300 C 10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
SYMBOL
IDD
VIH
VIL
IIH
IIL
IOH
Low Level Output Current
IOL
Output Rise & Fall Time
TR & TF
*IDD(Dynamic) = 2 * CLD * VDD * F
where: CLD = Average capacitance load/pin (pf)
F = Input frequency (GHz)
MIN
2.0
-4.0
4.0
MAX
40
0.8
1.0
1.0
2
UNITS
mA
V
V
µA
µA
mA
mA
ns
NOTES
VIH = VDD
VIL = 0V
VDD = 4.75V
VOH = 2.4V
VDD = 4.75V
VOL = 0.4V
CLD = 5 pf
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
TABLE 3: AC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
Input Baud Rate
Clock Frequency
Data set-up to clock rising
Data hold from clock rising
TX High-Low time skew
TXB High-Low time skew
TX - TXB High/Low time skew
SYMBOL
fBN
fC
tDS
tDH
t1H - t1L
t2H - t2L
t1H - t2L
MIN
3.5
0
-3.5
-2.0
-3.0
TYP
MAX
50
50
3.5
2.0
3.0
UNITS
MBaud
MHz
ns
ns
ns
ns
ns
Notes: 1: Assumes a 50% duty cycle clock input
NOTES
1
1
1
Doc #96010
5/19/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
3Pages | |||
ページ | 合計 : 4 ページ | ||
|
PDF ダウンロード | [ 3D7501D データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
3D7501 | MONOLITHIC MANCHESTER ENCODER | ETC |
3D7501D | MONOLITHIC MANCHESTER ENCODER | ETC |
3D7501G | MONOLITHIC MANCHESTER ENCODER | ETC |
3D7501H | MONOLITHIC MANCHESTER ENCODER | ETC |