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3972 の電気的特性と機能

3972のメーカーはAllegro MicroSystemsです、この部品の機能は「DUAL DMOS FULL-BRIDGE MICROSTEPPING PWM MOTOR DRIVER」です。


製品の詳細 ( Datasheet PDF )

部品番号 3972
部品説明 DUAL DMOS FULL-BRIDGE MICROSTEPPING PWM MOTOR DRIVER
メーカ Allegro MicroSystems
ロゴ Allegro MicroSystems ロゴ 




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3972 Datasheet, 3972 PDF,ピン配置, 機能
3972
VCP 1
CP1 2
CP2 3
OUT1B 4
LOAD
SUPPLY1 5 VBB1
GROUND 6
GROUND 7
SENSE1 8
OUT1A 99
STROBE 10
CLOCK 11
DATA 12
24 OSC
23 SLEEP
22 VREG
21 OUT2B
20 LOAD
VBB2
SUPPLY2
19 GROUND
18 GROUND
17 SENSE2
16 OUT2A
VDD
15
LOGIC
SUPPLY
14 MUX
13 REF
Dwg. PP-069-3
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB ................ 50 V
Output Current, IOUT ...................... ±1.5 A
Logic Supply Voltage, VDD .............. 7.0 V
Logic Input Voltage Range,
VIN ................ -0.3 V to VDD + 0.3 V
Reference Voltage, VREF ..................... 3 V
Sense Voltage (dc), VS ................ 500 mV
Package Power Dissipation,
PD .......................................... 3.1 W
Operating Temperature Range,
TA .......................... -20°C to +85°C
Junction Temperature, TJ ............. +150°C
Storage Temperature Range,
TS ......................... -55°C to +150°C
Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed the
specified current rating or a junction tempera-
ture of 150°C.
DUAL DMOS FULL-BRIDGE MICRO-
STEPPING PWM MOTOR DRIVER
Designed for pulse-width modulated (PWM) current control of
bipolar microstepping stepper motors, the A3972SB is capable of
continuous output currents to ±1.5 A and operating voltages to 50 V.
Internal fixed off-time PWM current-control timing circuitry can be
programmed via a serial interface to operate in slow, fast, and mixed
current-decay modes.
The desired load-current level is set via the serial port with two 6-bit
linear DACs in conjunction with a reference voltage. The six bits of
control allow maximum flexibility in torque control for a variety of step
methods, from microstepping to full-step drive. Load current is set in
1.56% increments of the maximum value.
Synchronous rectification circuitry allows the load current to flow
through the low rDS(on) of the DMOS output driver during the current
decay. This feature will eliminate the need for external clamp diodes in
most applications, saving cost and external component count, while
minimizing power dissipation.
Internal circuit protection includes thermal shutdown with hyster-
esis, transient-suppression diodes, and crossover-current protection.
Special power-up sequencing is not required.
The A3972SB is supplied in a 24-lead plastic DIP with a copper
batwing power tab (suffix ‘B’). The power tab is at ground potential and
needs no electrical isolation.
FEATURES
I ±1.5 A, 50 V Continuous Output Rating
I Low rDS(on) DMOS Output Drivers
I Optimized Microstepping via 6-Bit Linear DACs
I Programmable Mixed, Fast, and Slow Current-Decay Modes
I 4 MHz Internal Oscillator for Digital Timing
I Serial-Interface Controls Chip Functions
I Synchronous Rectification for Low Power Dissipation
I Internal UVLO and Thermal Shutdown Circuitry
I Crossover-Current Protection
I Precision 2 V Reference
I Inputs Compatible with 3.3 V or 5 V Control Signals
I Sleep and Idle Modes
Always order by complete part number: A3972SB .

1 Page





3972 pdf, ピン配列
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VS = 0.5 V,
fPWM < 50 kHz (unless otherwise noted).
Limits
Characteristic
Symbol Test Conditions
Min. Typ. Max.
Load Supply Voltage Range
VBB Operating
During sleep mode
15 — 50
0 — 50
Logic Supply Voltage Range
Load Supply Current
VDD Operating
IBB fPWM < 50 kHz
Operating, outputs disabled
4.5 5.0 5.5
— — 8.0
— — 6.0
Sleep or idle mode
— — 20
Logic Supply Current
IDD fPWM < 50 kHz
Outputs off
— — 12
— — 10
Idle mode (D0 = 1, D18 = 0)
— — 1.5
Sleep mode
— — 100
Output Drivers
Output Leakage Current
Output On Resistance
Body Diode Forward Voltage
Control Logic
IDSS
rDS(on)
VF
VOUT = VBB
VOUT = 0 V
Source driver, IOUT = –1.5 A
Sink driver, IOUT = 1.5 A
Source diode, IF = 1.5 A
Sink diode, IF = 1.5 A
— <1.0 50
— <-1.0 -50
— 0.5 0.55
— 0.315 0.35
— — 1.2
— — 1.2
Logic Input Voltage
Logic Input Current
OSC Input Frequency Range
VIN(1)
VIN(0)
IIN(1)
IIN(0)
fOSC
VIN = 2.0 V
VIN = 0.8 V
Divide by one
(D0 =1, D13 = 0, D14 = 1)
2.0 —
— — 0.8
— <1.0 20
— <-2.0 -20
2.5 — 6.0
OSC Input Duty Cycle
40 — 60
Input Hysterisis
VIN
0.20 — 0.40
Units
V
V
V
mA
mA
µA
mA
mA
mA
µA
µA
µA
V
V
V
V
µA
µA
MHz
%
V
continued next page ...
www.allegromicro.com
3


3Pages


3972 電子部品, 半導体
3972
DUAL DMOS FULL-BRIDGE
MICROSTEPPING PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
Word 1 Bit Assignments
Bit Function
D0 Word select = 1
D1 Blank-time LSB
D2 Blank-time MSB
D3 Off-time LSB
D4 Off-time bit 1
D5 Off-time bit 2
D6 Off-time bit 3
D7 Off-time MSB
D8 Fast-decay time LSB
D9 Fast-decay time bit 1
D10 Fast-decay time bit 2
D11 Fast-decay time MSB
D12 C0 oscillator control
D13 C1 oscillator control
D14 SR control bit 1
D15 SR control bit 2
D16 Reserved for testing
D17 Reserved for testing
D18 Idle mode
D1 – D2 Blank Time. These two bits set the blank time for
the current-sense comparator. When a source driver turns on, a
current spike occurs due to the reverse-recovery currents of the
clamp diodes and/or switching transients related to distributed
capacitance in the load. To prevent this current spike from
erroneously resetting the source-enable latch, the sense com-
parator is blanked. The blank timer runs after the off-time
counter to provide the programmable blanking function. The
blank timer is reset when PHASE is changed.
D2 D1 Time
0 0 4/fOSC
0 1 6/fOSC
1 0 8/fOSC
1 1 12/fOSC
D3 – D7 Fixed Off Time. These five bits set the fixed off-
time for the internal PWM control circuitry. Fixed off-time is
defined by:
toff = [(1 + N) x 8/fOSC] - 1/fOSC
where N = 0.31
For example, with a master oscillator frequency of 4 MHz, the
fast-decay time will be adjustable from 1.75 µs to 63.75 µs in
increments of 2 µs.
D8 – D11 Fast Decay Time. These four bits set the fast-
decay portion of fixed off-time for the internal PWM control
circuitry. The fast-decay portion is defined by:
tfd = [(1 + N) x 8/fOSC] - 1/fOSC
where N = 0.15
For example, with an oscillator frequency of 4 MHz, the fast-
decay time will be adjustable from 1.75 µs to 31.75 µs in
increments of 2 µs. For tfd > toff , the device will effectively
operate in fast-decay mode.
D12 – D13 Oscillator Control. A 4 MHz internal oscillator
is used for the timing functions and charge-pump clock. If
more precise control is required, an external oscillator can be
input to the OSC terminal. To accommodate a wider range of
system clocks, an internal divider is provided to generate the
desired MO frequency according to the following table:
D13 D12
00
01
10
11
OSC
4 MHz internal clock
External clock
External clock/2
External clock/4
D14 – D15 Synchronous Rectification.
D15 D14
00
01
10
11
Synchronous Rectifier
Active
Disabled
Passive
Low side only
The different modes of operation are in the synchronous
rectification section of the functional description.
D16, D17. These bits are reserved for testing and should be
programmed to zero during normal operation.
D18 Idle Mode. The device can be placed in a low power
idlemode by writing a 0to D18. The outputs will be
disabled, the charge pump will be turned off, and the device
will draw a lower load supply currrent. The undervoltage
monitor circuit will remain active. D18 should be programmed
high for 1 ms before attempting to enable any output driver.
continued next page ...
115 Northeast Cutoff, Box 15036
6 Worcester, Massachusetts 01615-0036 (508) 853-5000

6 Page



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