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3948 の電気的特性と機能

3948のメーカーはAllegro MicroSystemsです、この部品の機能は「DMOS FULL-BRIDGE PWM MOTOR DRIVER」です。


製品の詳細 ( Datasheet PDF )

部品番号 3948
部品説明 DMOS FULL-BRIDGE PWM MOTOR DRIVER
メーカ Allegro MicroSystems
ロゴ Allegro MicroSystems ロゴ 




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3948 Datasheet, 3948 PDF,ピン配置, 機能
3948
A3948SLB (SOIC)
CP 1
CP2 2
CP1 3
PHASE 4 θ
OSC 5
GROUND 6
GROUND 7
LOGIC SUPPLY 8 VDD
ENABLE 99
DATA 10
CLOCK 11
STROBE 12
24 VREG
23 RANGE
NC 22
NO
CONNECTION
21 OUTB
VBB 20 LOAD SUPPLY
19 GROUND
18 GROUND
17 SENSE
16 OUTA
NC 15
NO
CONNECTION
14 MODE
÷ 13 REF
Dwg. PP-069A
Note that the A3948SLB(SOIC) and A3948SB
(DIP) do not share a common terminal
assignment.
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB .................. 50 V
Output Current, IOUT ........................ ±1.5 A
Logic Supply Voltage, VDD ................ 7.0 V
Input Voltage, VIN .... -0.3 V to VDD + 0.3 V
Sense Voltage, VS .......................... 0.55 V
Reference Voltage, VREF .................. 5.5 V
Package Power Dissipation (TA = 25°C), PD
A3948SB ................................. 3.1 W*
A3948SLB ............................... 1.6 W*
Operating Temperature Range,
TA ............................... -20°C to +85°C
Junction Temperature,
TJ ............................................ +150°C
Storage Temperature Range,
TS ............................. -55°C to +150°C
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified
current rating or a junction temperature of 150°C.
* Per SEMI G42-88 Specification.
DMOS FULL-BRIDGE PWM
MOTOR DRIVER
Designed for pulse-width modulated (PWM) current control of dc
motors, the A3948SB and A3948SLB are capable of continuous output
currents to ±1.5 A and operating voltages to 50 V. Internal fixed off-
time PWM current-control timing circuitry can be programmed via a
serial interface to operate in slow, fast, and mixed current-decay
modes. Similar devices with outputs rated to ±2 A are available as the
A3958SB/SLB.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM-control signals. The ENABLE input can be
programmed via the serial port to PWM the bridge in fast or slow
current decay. Internal synchronous rectification control circuitry is
provided to reduce power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, and crossover-current protection. Special power-up
sequencing is not required.
The A3948SB/SLB is supplied in a choice of two power
packages, a 24-pin plastic DIP with a copper batwing tab (package
suffix ‘B’), and a 24-lead plastic SOIC with a copper batwing tab
(package suffix ‘LB’). In both cases, the power tab is at ground
potential and needs no electrical isolation.
FEATURES
s ±1.5 A, 50 V Continuous Output Rating
s Low rDS(on) Outputs
s Programmable Mixed, Fast, and Slow Current-Decay Modes
s Serial Interface Controls Chip Functions
s Synchronous Rectification for Low Power Dissipation
s Internal UVLO and Thermal-Shutdown Circuitry
s Crossover-Current Protection
Always order by complete part number:
Part Number
Package
A3948SB
24-pin batwing DIP
A3948SLB
24-lead batwing SOIC
RθJA
40°C/W
77°C/W
RθJT
6°C/W
6°C/W

1 Page





3948 pdf, ピン配列
3948
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V,
fPWM < 50 kHz (unless noted otherwise)
Limits
Characteristics
Symbol Test Conditions
Min. Typ. Max. Units
Output Drivers
Load Supply Voltage Range
VBB Operating
During sleep mode
20 – 50
0 – 50
V
V
Output Leakage Current
Output On Resistance
Body Diode Forward Voltage
Load Supply Current
IDSS
rDS(on)
VF
IBB
VOUT = VBB
VOUT = 0 V
Source driver, IOUT = -1.5 A
Sink driver, IOUT = 1.5 A
Source diode, IF = -1.5 A
Sink diode, IF = 1.5 A
fPWM < 50 kHz
Charge pump on, outputs disabled
– <1.0 20
– <-1.0 -20
– 500 550
– 300 350
– 1.0 1.3
– 1.0 1.3
– 4.0 7.0
– 2.0 5.0
µA
µA
m
m
V
V
mA
mA
Sleep Mode
– – 20 µA
Control Logic
Logic Supply Voltage Range
Logic Input Voltage
Logic Input Current
(all inputs except ENABLE)
ENABLE Input Current
OSC input frequency
OSC input duty cycle
OSC input hysteresis
VDD
VIN(1)
VIN(0)
IIN(1)
IIN(0)
IIN(1)
IIN(0)
fOSC
dcOSC
Operating
VIN = 2.0 V
VIN = 0.8 V
VIN = 2.0 V
VIN = 0.8 V
Operating
Operating
Operating
4.5 5.0 5.5
2.0 – –
– – 0.8
– <1.0 20
– <-2.0 -20
– 40 100
– 16 40
1.8 – 6.1
40 – 60
200 – 400
V
V
V
µA
µA
µA
µA
MHz
%
mV
Input Hysterisis
– All digital inputs except OSC
50 – 100 mV
Reference Input Volt. Range
Reference Input Current
Comparator Input Offset Volt.
VREF
IREF
VIO
Operating
VREF = 2.5 V
VREF = 0 V
0.0 – VDD - 0.1 V
– – ±0.5 µA
– 0 ±5.0 mV
Continued next page …
www.allegromicro.com
3


3Pages


3948 電子部品, 半導体
3948
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
D15 Phase Logic. Bit D15, in conjunction with
PHASE, determines if the device is operating in the
forward (PHASE D15) or reverse (PHASE = D15) state.
PHASE D15
00
10
01
11
State
Reverse
Forward
Forward
Reverse
OUTA
Low
High
High
Low
OUTB
High
Low
Low
High
D16 Gm Range Select. Bit D16, in conjunction with
RANGE, determines if VREF is divided by 5 (RANGE
D16) or by 10 (RANGE = D16).
RANGE D16 Divider
0 0 ÷10
1 0 ÷5
0 1 ÷5
1 1 ÷10
D17 Internal PWM Mode. Bit D17, in conjunction with
MODE, selects slow (MODE D17) or mixed (MODE =
D17) current decay.
MODE D17
00
10
01
11
Current-Decay Mode
Mixed
Slow
Slow
Mixed
D18 Test Mode. Bit D18 low (default) operates the
device in normal mode. D18 is only used for testing
purposes. The user should never change this bit.
D19 Sleep Mode. Bit D19 selects a Sleep mode to
minimize power consumption when not in use. This
disables much of the internal circuitry including the
regulator and charge pump. On power up the serial port is
initialized to all 0s. Bit D19 should be programmed high
for 1 ms before attempting to enable any output driver.
D19 Sleep Mode
0 Sleep
1 Normal
Serial Port Write Timing Operation. Data is clocked
into the shift register on the rising edge of the CLOCK
signal. Normally STROBE will be held high, only
brought low to initiate a write cycle. Refer to diagram
below and these specifications for the minimum timing
requirements.
A.DATA setup time ......................................... 15 ns
B.DATA hold time ........................................... 10 ns
C.Setup STROBE to CLOCK rising edge ....... 50 ns
D.CLOCK high pulse width ............................ 50 ns
E.CLOCK low pulse width .............................. 50 ns
F.Setup CLOCK rising edge to STROBE ....... 50 ns
G.STROBE pulse width ................................... 50 ns
STROBE
CLOCK
DATA
Serial Port Write Timing
CD
AB
D19
E
D18
F
D0
G
Dwg. WP-038
115 Northeast Cutoff, Box 15036
6 Worcester, Massachusetts 01615-0036 (508) 853-5000

6 Page



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