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37LV128-SN の電気的特性と機能

37LV128-SNのメーカーはMicrochip Technologyです、この部品の機能は「36K/ 64K/ and 128K Serial EPROM Family」です。


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部品番号 37LV128-SN
部品説明 36K/ 64K/ and 128K Serial EPROM Family
メーカ Microchip Technology
ロゴ Microchip Technology ロゴ 




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37LV128-SN Datasheet, 37LV128-SN PDF,ピン配置, 機能
37LV36/65/128
36K, 64K, and 128K Serial EPROM Family
FEATURES
• Operationally equivalent to Xilinx® XC1700 family
• Wide voltage range 3.0 V to 6.0 V
• Maximum read current 10 mA at 5.0 V
• Standby current 100 µA typical
• Industry standard Synchronous Serial Interface/
1 bit per rising edge of clock
• Full Static Operation
• Sequential Read/Program
• Cascadable Output Enable
• 10 MHz Maximum Clock Rate @ 5.0 Vdc
• Programmable Polarity on Hardware Reset
• Programming with industry standard EPROM pro-
grammers
• Electrostatic discharge protection > 4,000 volts
• 8-pin PDIP/SOIC and 20-pin PLCC packages
• Data Retention > 200 years
• Temperature ranges:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 37LV36/65/128 is a
family of Serial OTP EPROM devices organized inter-
nally in a x32 configuration. The family also features a
cascadable option for increased memory storage
where needed. The 37LV36/65/128 is suitable for
many applications in which look-up table information
storage is desirable and provides full static operation in
the 3.0V to 6.0V VCC range. The devices also support
the industry standard serial interface to the popular
RAM-based Field Programmable Gate Arrays (FPGA).
Advanced CMOS technology makes this an ideal boot-
strap solution for today's high speed SRAM-based
FPGAs. The 37LV36/65/128 family is available in the
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin
PLCC packages.
Device Bits Programming Word
37LV36
37LV65
37LV128
36,288
65,536
131,072
1134 x 32
2048 x 32
4096 x 32
Xilinx is a registered trademark of Xilinx Corporation.
PACKAGE TYPES
PDIP
DATA 1
CLK 2
RESET/OE 3
CE 4
8 VCC
7 VPP
6 CEO
5 VSS
SOIC
DATA
CLK
RESET/OE
CE
PLCC
18
27
36
45
DATA VCC
VCC
VPP
CEO
VSS
CLK 4
5
RESET/OE 6
7
CE 8
18
17 VPP
16
15
14 CEO
Vss
BLOCK DIAGRAM
CE
RESET/OE
CEO
ADDRESS EPROM
Counter ARRAY
CLK
OE
DATA
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS21109E-page 1

1 Page





37LV128-SN pdf, ピン配列
2.0 DATA
2.1 Data I/O
Three-state DATA output for reading and input during
programming.
3.0 CLK
3.1 Clock Input
Used to increment the internal address and bit
counters for reading and programming.
4.0 RESET/OE
4.1 Reset Input and Output Enable
A LOW level on both the CE and RESET/OE inputs
enables the data output driver. A HIGH level on
RESET/OE resets both the address and bit counters.
In the 37LVXXX, the logic polarity of this input is pro-
grammable as either RESET/OE or OE/RESET. This
document describes the pin as RESET/OE although
the opposite polarity is also possible. This option is
defined and set at device program time.
5.0 CE
5.1 Chip Enable Input
CE is used for device selection. A LOW level on both
CE and OE enables the data output driver. A HIGH
level on CE disables both the address and bit counters
and forces the device into a low power mode.
6.0 CEO
6.1 Chip Enable Output
This signal is asserted LOW on the clock cycle follow-
ing the last bit read from the memory. It will stay LOW
as long as CE and OE are both LOW. It will then follow
CE until OE goes HIGH. Thereafter, CEO will stay
HIGH until the entire EPROM is read again. This pin
also used to sense the status of RESET polarity when
Programming Mode is entered.
7.0 VPP
7.1 Programming Voltage Supply
Used to enter programming mode (+13 volts) and to
program the memory (+13 volts). Must be connected
directly to Vcc for normal Read operation. No over-
shoot above +14 volts is permitted.
37LV36/65/128
8.0 CASCADING SERIAL EPROMS
Cascading Serial EPROMs provide additional memory
for multiple FPGAs configured as a daisy-chain, or for
future applications requiring larger configuration mem-
ories.
When the last bit from the first Serial EPROM is read,
the next clock signal to the Serial EPROM asserts its
CEO output LOW and disables its DATA line. The sec-
ond Serial EPROM recognizes the LOW level on its CE
input and enables its DATA output.
When configuration is complete, the address counters
of all cascaded Serial EPROMs are reset if RESET
goes LOW forcing the RESET/OE on each Serial
EPROM to go HIGH. If the address counters are not to
be reset upon completion, then the RESET/OE inputs
can be tied to ground.
Additional logic may be required if cascaded memories
are so large that the rippled chip enable is not fast
enough to activate successive Serial EPROMs.
9.0 STANDBY MODE
The 37LVXXX enters a low-power Standby Mode
whenever CE is HIGH. In Standby Mode, the Serial
EPROM consumes less than 100 µA of current. The
output will remain in a high-impedance state regardless
of the state of the OE input.
10.0 PROGRAMMING MODE
Programming Mode is entered by holding VPP HIGH
(+13 volts) for two clock edges and then holding VPP =
VDD for one clock edge. Programming mode is exited
by driving a LOW on both CE and OE and then remov-
ing power from the device. Figures 4 through 7 show
the programming algorithm.
11.0 37LVXXX RESET POLARITY
The 37LVXXX lets the user choose the reset polarity as
either RESET/OE or OE/RESET. Any third-party com-
mercial programmer should prompt the user for the
desired reset polarity.
The programming of the overflow word should be han-
dled transparently by the EPROM programmer; it is
mentioned here as supplemental information only.
The polarity is programmed into the first overflow word
location, maximum address+1. 00000000 in these
locations makes the reset active LOW, FFFFFFFF in
these locations makes the reset active HIGH. The
default condition is RESET active HIGH.
© 1996 Microchip Technology Inc.
DS21109E-page 3


3Pages


37LV128-SN 電子部品, 半導体
37LV36/65/128
TABLE 11-3: PIN ASSIGNMENTS IN THE PROGRAMMING MODE
DIP/SOIC
Pin
PLCC Pin
Name
I/O
Description
1
2
DATA
I/O The rising edge of the clock shifts a data word in or out of the
EPROM one bit at a time.
2 4 CLK I Clock Input. Used to increment the internal address/word
counter for reading and programming operation.
3 6 RESET/OE I The rising edge of CLK shifts a data word into the EPROM
when CE and OE are HIGH; it shifts a data word out of the
EPROM when CE is LOW and OE is HIGH. The address/
word counter is incremented on the rising edge of CLK while
CE is held HIGH and OE is held LOW.
Note 1: Any modified polarity of the RESET/OE pin is
ignored in the programming mode.
4 8 CE I The rising edge of CLK shifts a data word into the EPROM
when CE and OE are HIGH; it shifts a data word out of the
EPROM when CE is LOW and OE is HIGH. The address/
word counter is incremented on the rising edge of CLK while
CE is held HIGH and OE is held LOW.
5 10 VSS
Ground pin.
6 14 CEO O The polarity of the RESET/OE pin can be read by sensing the
CEO pin.
Note 1: The polarity of the RESET/OE pin is ignored while in
the Programming Mode. In final verification, this pin
must be monitored to go LOW one clock cycle after
the last data bit has been read.
7 17 VPP
Programming Voltage Supply. Programming Mode is entered
by holding CE and OE HIGH and VPP at VPP1 for two rising
clock edges and then lowering VPP to VPP2 for one more ris-
ing clock edge. A word is programmed by strobing the device
with VPP for the duration TPGM. VPP must be tied to VCC for
normal read operation.
8 20 VCC
+5 V power supply input.
DS21109E-page 6
© 1996 Microchip Technology Inc.

6 Page



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部品番号部品説明メーカ
37LV128-SN

36K/ 64K/ and 128K Serial EPROM Family

Microchip Technology
Microchip Technology


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