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30171-53 の電気的特性と機能

30171-53のメーカーはNational Semiconductorです、この部品の機能は「Geode GXLV Processor Series Low Power Integrated x86 Solutions」です。


製品の詳細 ( Datasheet PDF )

部品番号 30171-53
部品説明 Geode GXLV Processor Series Low Power Integrated x86 Solutions
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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30171-53 Datasheet, 30171-53 PDF,ピン配置, 機能
April 2000
Geode™ GXLV Processor Series
Low Power Integrated x86 Solutions
General Description
The National Semiconductor® Geode™ GXLV processor
series is a new line of integrated processors specifically
designed to power information appliances for entertain-
ment, education, and business. Serving the needs of con-
sumers and business professionals alike, it is the perfect
solution for information appliance applications such as
thin clients, interactive set top boxes, and personal inter-
net access devices.
The GXLV processor series is divided into three main cat-
egories as defined by the core operating voltage. Avail-
able with core voltages of 2.2V, 2.5V, and 2.9V, it offers
extremely low typical power consumption (1.0W to 2.5W)
leading to longer battery life and enabling small form-fac-
tor, fanless designs. Each core voltage is offered in fre-
quencies that are enabled by specific system clock and
multiplier settings. This allows the user to select the
device(s) that best fit their power and performance
requirements. This flexibility makes the GXLV processor
series ideally suited for applications where power con-
sumption and performance (speed) are equally important.
Typical power consumption is defined as an average,
measured running Microsoft’s Windows at 80% Active Idle
(Suspend-on-Halt) with a display resolution of 800x600x8
bpp at 75 Hz.
Internal Block Diagram
SYSCLK
Clock Module
SYSCLK
multiplied by
A
Core
Clocks
X-Bus
Clocks
16 KB
Unified L1
Cache
(128)
X86 Compatible Core
Integer
TLB Unit
Instruction
Fetch
MMU
Load/Store
INT/NMI
Interrupt
Control
FP_Error
Floating Point
Unit
INTR
IRQ13
SMI#
C-Bus (64)
SUSP#
SUSPA#
Power
Management
Control
Core Suspend
Core Acknowledge
X-Bus Suspend
X-Bus Acknowledge
X-Bus (32)
Arbiter
Write Buffers
X-Bus Controller
Read Buffers
PCI Host
Arbiter Controller
2D Accelerator
VGA
BLT Engine
ROP Unit
X-Bus Clk ÷ B
Display Controller
Compression Buffer
Palette RAM
Timing Generator
3
REQ/GNT
Pairs
PCI Bus
4
SDRAM
Clocks
64-bit SDRAM
RGB
YUV
Video Companion Interface
National Semiconductor is a registered trademark of National Semiconductor Corporation.
Geode and WebPAD are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2000 National Semiconductor® Corporation
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30171-53 pdf, ピン配列
PCI Host Controller
 Several arbitration schemes supported
 Supports up to three PCI bus masters
 Synchronous to CPU core
 Allows external PCI master accesses to main memory
concurrent with CPU accesses to L1 cache
Virtual Systems Architecture Technology
 Innovative architecture allowing OS independent (soft-
ware) virtualization of hardware functions
 Provides XpressGRAPHICS subsystem:
— High performance legacy VGA core compatibility
Note: Uses 2D Graphics Accelerator.
 Provides 16-bit XpressAUDIO subsystem:
— 16-bit stereo FM synthesis
— OPL3 emulation
— Supports MPU-401 MIDI interface
— Hardware assist provided via Geode I/O companion
chip
 Additional hardware functions can be supported as
needed
2D Graphics Accelerator
 Accelerates BitBLTs, line draw, text
 Bresenham vector engine
 Supports all 256 ROPs
 Supports transparent BLTs and page flipping for
Microsoft’s DirectDraw
 Runs at core clock frequency
 Full VGA and VESA mode support
 Special "driver level” instructions utilize internal
scratchpad for enhanced performance
Display Controller
 Display Compression Technology (DCT) architecture
greatly reduces memory bandwidth consumption of
display refresh
 Supports a separate video buffer and data path to
enable video acceleration in Geode I/O companion
devices
 Internal palette RAM for gamma correction
 Direct interface to Geode I/O companion devices for
CRT and TFT flat panel support eliminates the need for
an external RAMDAC
 Hardware cursor
 Supports up to 1280x1024x8 bpp and
1024x768x16 bpp
XpressRAM Subsystem
 SDRAM interface tightly coupled to CPU core and
graphics subsystem for maximum efficiency
 64-Bit wide memory bus
 Support for:
— Two 168-pin unbuffered DIMMs
— Up to 16 simultaneously open banks
— 16-byte reads (burst length of two)
— Up to 256 MB total memory supported
Diverse Operating System Support
 Microsoft’s Windows 2000, 9X, NT, and CE
 Sun Microsystems’ Java
 WindRiver Systems’ VxWorks
 QNX Software Systems’ QNX
 Linux
Revision 1.1
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30171-53 電子部品, 半導体
Table of Contents (Continued)
4.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.1 INTEGRATED FUNCTIONS PROGRAMMING INTERFACE . . . . . . . . . . . . . . . . . . . . . . . 97
4.1.1 Graphics Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1.3 Graphics Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1.4 Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.1 Initialization of Scratchpad RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.2 Scratchpad RAM Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.4.3 BLT Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1.5 Display Driver Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.1.6 CPU_READ/CPU_WRITE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2 INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.1 FPU Error Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.2 A20M Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.3 SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.4 640 KB to 1 MB Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.5 Internal Bus Interface Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.3 MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
Memory Array Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Memory Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.3.3.1 SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Memory Controller Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.1 High Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.2 Auto Low Order Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.3.5.3 Physical Address to DRAM Address Conversion . . . . . . . . . . . . . . . . . . . . . . . . 117
Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SDRAM Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.4 GRAPHICS PIPELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
BitBLT/Vector Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Master/Slave Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.4.3.1 Monochrome Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.3.2 Dither Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.4.3.3 Color Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Source Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Graphics Pipeline Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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共有リンク

Link :


部品番号部品説明メーカ
30171-53

Geode GXLV Processor Series Low Power Integrated x86 Solutions

National Semiconductor
National Semiconductor
30171-53

Geode GXm Processor Integrated x86 Solution with MMX Support

National Semiconductor
National Semiconductor


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