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PDF CXD8302Q Data sheet ( Hoja de datos )
| Número de pieza | CXD8302Q | |
| Descripción | PLL for CCD Cameras | |
| Fabricantes | Sony Corporation | |
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CXD8302Q
PLL for CCD Cameras
For the availability of this product, please contact the sales office.
Description
The CXD8302Q has the functions needs to
configure a PLL circuit with a timing generator and
external sync signals for a CCD of 480K pixels (EIA,
effective pixels) and 570K pixels (CCIR, effective
pixels).
44 pin QFP (Plastic)
Features
• EIA and CCIR compatible
• Compatible with component digital and composite
digital recording format
• Both SYNC and VD/HD signals can be used for
external sync signals
Applications
CCD cameras
Absolute Maximum Ratings
• Supply voltage
VDD VSS – 0.3 to +7 V
• Input voltage
VI VSS – 0.3 to VDD+0.3 V
• Storage temperature Tstg –40 to +125 °C
Structure
Silicon gate CMOS IC
Recommended Operating Conditions
• Supply voltage
VDD 4.5 to 5.5
• Operating temperature Topr
0 to 70
V
°C
Block Diagram
EXTSYNC 15
EXTHD 14
EXTVD 13
fH
Separation
of fH and fV
fV
65 Clocks
Delay
V reset
19 EXTfH
V latch
MODE1 26
MODE2 31
EIA/CCIR 32
Frequency Division
EIA : 1/572
(1/568)
CCIR: 1/576
(1/567)
2fH
H timing
Frequency Division
EIA : 1/525
CCIR: 1/625
V timing
20 INTfH
41 HD
42 VD
43 SYNC
44 BLK
CLKI 38
8
2 3 4 7 8 9 10 11
INTfH phase setting
37 CLKO
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94320A52-PP
1 page  
CXD8302Q
3) I/O pin capacitance (VDD = 5V±0.25V, Topr = 0 to 70°C, VSS = 0V)
Item Symbol
Input pin capacitance CIN
Output pin capacitance COUT
Min.
Typ.
2.0
4.0
Max.
Unit
pF
pF
Description of Operation
1) Operation overview
• Functions as sync signal generator
Each of fH (INTfH), VD, HD, SYNC, and BLK pulses is generated from clocks input by the timing generator.
These pulses are generated by free running if external sync signals are not input.
• External synchronization function (PLL)
When the SYNC (EXTSYNC) or VD/HD (EXTVD/EXTHD) external sync signal is input, the vertical reset is
compulsorily triggered on each of the fH (INTfH), VD, HD, SYNC, and BLK pulses, and fH (EXTfH) is
simultaneously generated according to the external sync signal. Phase comparison is done externally
between INTfH and EXTfH and a PLL circuit is configured, then the timing generator is synchronized with an
external sync signal.
2) Mode setting
Symbol Pin No.
L
EIA/CCIR 32
CCIR
MODE1
VD/HD sync mode:
26
EXTVD/EXTHD is used as the external
sync signal, and the EXTHD signal
becomes EXTfH.
MODE2
Composite digital mode;
Clock frequency input by timing generator
31 EIA 17.897725MHz (1137.5fH = 5fsc)
CCIR 17.734475MHz
(1135 + 4/625fH = 4fsc)
H
EIA
SYNC sync mode:
EXTSYNC is used as the external sync
signal, and the EXTfH is obtained by
separating it from EXTSYNC
Component digital mode:
Clock frequency input by timing generator
EIA 18MHz (1144fH)
CCIR 18MHz (1152fH)
The phase relationship between external sync and EXTfH in each sync mode is shown below.
• VD/HD sync mode
The rise and fall timings of EXTHD signal are directly reflected on EXTfH.
EXTHD
EXTfH
• SYNC synchronous mode
The fall timing of EXTSYNC is the fall timing EXTfH, but the rise timing of EXTfH is generated by counting the
number of clocks input by the timing generator. Therefore, make sure to compare phases of fall timing of
between EXTfH and INTfH for PLL configuration in the SYNC synchronous mode.
EXTSYNC
(HSYNC)
EXTfH
42 clocks
–5–
42 clocks
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CXD8302Q.PDF ] | |
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