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PDF CXD2548R Data sheet ( Hoja de datos )
| Número de pieza | CXD2548R | |
| Descripción | CD Digital Signal Processor with Built-in Digital Servo and DAC | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD2548R
CD Digital Signal Processor with Built-in Digital Servo and DAC
For the availability of this product, please contact the sales office.
Description
The CXD2548R is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter, zero detection circuit, 1-bit DAC and
analog low-pass filter on a single chip.
112 pin LQFP (Plastic)
Features
• All digital signal processing during playback is
performed with a single chip
• Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor (DSP) Block
• Playback mode which supports CAV (Constant
Angular Velocity)
• Frame jitter free
• 0.5 × to 2.5 × continuous playback possible
• Allows relative rotational velocity readout
• Supports spindle external control
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports normal-speed, double-speed playback
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry compensation circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Digital audio interface outputs
• Digital level meter, peak meter
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
Digital Filter, DAC and Analog Low-Pass Filter Blocks
• Digital de-emphasis
• Digital attenuation
• Zero detection function
• 8Fs oversampling digital filter
• S/N: 100dB or more (master clock: 384Fs, typ.)
• THD + N: 0.007% or more (master clock: 384Fs,
typ.)
• Rejection band attenuation: –60dB or more
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage
VDD
–0.3 to +7.0 V
• Input voltage
VI
–0.3 to +7.0 V
(VSS – 0.3V to VDD + 0.3)
• Output voltage
VO
–0.3 to +7.0 V
• Storage temperature Tstg
–40 to +125 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Recommended Operating Conditions
• Supply voltage
VDDNote) –3.4 to +5.25 V
• Operating temperature Topr
–20 to +75 °C
Note) The VDD (Min.) for the CXD2548R varies
according to the playback speed selection.
Playback
VDD (min.) [V]
speed CD-DSP block DAC block DSSP block
2×
3.4V
4.5V
3.4V
1×
1 ×∗1
3.4V
3.4V
3.4V
3.4V
3.4V
∗1 When the internal operation of the CD-DSP side
is set to double-speed mode and the crystal
oscillation frequency is halved, normal-speed
playback results.
I/O Capacitance
• Input pin
• Output pin
CI
CO
12 (Max.) pF
12 (Max.) pF
Note) Measurement conditions VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96404-PS
1 page  
CXD2548R
Pin
No.
Symbol
I/O
Description
37 FOK
O 1, 0 Focus OK signal output.
38 VDD1
Digital power supply.
39 VPCO1 O 1, Z, 0 Wide-band EFM PLL charge pump output.
40 VPCO2 O 1, Z, 0 Wide-band EFM PLL VCO2 charge pump output.
41 VCKI
I
Wide-band EFM PLL VCO2 oscillation input.
42 V16M
O 1, 0 Wide-band EFM PLL VCO2 oscillation output.
43 VCTL
I
Wide-band EFM PLL VCO2 control input.
44 PCO
O 1, Z, 0 Master PLL charge pump output.
45 FILO
O Analog Master PLL filter output (slave = digital PLL).
46 FILI
I
Master PLL filter input.
47 AVss4
Analog GND.
48 CLTV
I
Master VCO control voltage input.
49 AVDD4
Analog power supply.
50 RFAC
I
EFM signal input.
51 BIAS
I
Asymmetry circuit constant current input.
52 ASYI
I
Asymmetry comparator voltage input.
53 ASYO
O 1, 0 EFM full-swing output (low = VSS, high = VDD).
54 VC
I
Center voltage input.
55 FE
I
Focus error signal input.
56 SE
I
Sled error signal input.
57 TE
I
Tracking error signal input.
58 CE
I
Center error signal input.
59 RFDC
I
RF signal input. Input range: 2.15 to 5.0V. (when DVDD = AVDD = 5.0V)
60 RFC
I
Connects an RF signal LPF time-constant capacitor.
61 ADIO
O
Operational amplifier output.
62 AVss3
Analog GND.
63 IGEN
I
Connects an operational amplifier current source reference resistor.
64 AVDD3
Analog power supply.
65 TES2
I
Test pin. Normally fixed to low.
66 TES3
I
Test pin. Normally fixed to low.
67 Vss2
Digital GND.
68 TEST
I
Test pin. Normally fixed to low.
69 SFDR O 1, 0 Sled drive output.
70 SRDR O 1, 0 Sled drive output.
71 TFDR
O 1, 0 Tracking drive output.
72 TRDR O 1, 0 Tracking drive output.
73 FFDR
O 1, 0 Focus drive output.
–5–
5 Page 
(4) SCLK pin
XLAT
SCLK
Serial Read Out Data
(SENS)
tDLS
tSPW
1/fSCLK
MSB
···
···
Item
SCLK frequency
SCLK pulse width
Delay time
Symbol
fSCLK
tSPW
tDLS
Min.
500
15
Typ.
Max.
1
Unit
MHz
ns
µs
CXD2548R
LSB
(5) COUT, MIRR and DFCT pins
Operating frequency (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit Conditions
COUT maximum
operating frequency
fCOUT
40
kHz ∗1
MIRR maximum
operating frequency
fMIRR
40
kHz ∗2
DFCT maximum
operating frequency
fDFCTH
5
kHz ∗3
∗1 When using a high-speed traverse TZC
∗2
B
A
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.6 to 1.3V
• B = 25% or less
A+B
∗3 During complete RF signal omission
When settings related to DFCT signal generation are Typ.
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD2548R.PDF ] | |
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