PDF CYM1831PM-25C Data sheet ( Hoja de datos )

Número de pieza	CYM1831PM-25C
Descripción	64K x 32 Static RAM Module
Fabricantes	Cypress Semiconductor
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No Preview Available ! 31 CYM1831 Features • High-density 2-Mbit SRAM module • 32-bit standard footprint supports densities from 16K x 32 through 1M x 32 • High-speed CMOS SRAMs — Access time of 15 ns • Low active power — 5.3W (max.) • SMD technology • TTL-compatible inputs and outputs • Low profile — Max. height of 0.50 in. • Small PCB footprint — 1.2 sq. in. Functional Description The CYM1831 is a high-performance 2-Mbit static RAM mod- ule organized as 64K words by 32 bits. This module is con- structed from eight 64K x 4 SRAMs in SOJ packages mounted 64K x 32 Static RAM Module on an epoxy laminate board with pins. Four chip selects (CS1, CS2, CS3, and CS4) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Writing to each byte is accomplished when the appropriate Chip Selects (CSN) and Write Enable (WE) inputs are both LOW. Data on the input/output pins (I/OX) is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Selects (CSN) LOW and Output Enable (OE) LOW while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data input/output pins (I/OX). The data input/output pins stay in the high-impedance state when Write Enable (WE) is LOW or the appropriate chip se- lects are HIGH. Two pins (PD0 and PD1) are used to identify module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged. Logic Block Diagram A0 –A15 OE WE 16 CS1 CS2 CS3 CS4 64K x 4 SRAM 4 I/O0 – I/O3 64K x 4 SRAM 4 I/O8 – I/O11 64K x 4 SRAM 4 I/O16 – I/O19 64K x 4 SRAM 4 I/O24 – I/O27 Pin Configuration ZIP/SIMM Top View PD0 - OPEN PD1 - GND 64K x 4 SRAM 4 I/O4– I/O7 64K x 4 SRAM 4 I/O12– I/O15 64K x 4 SRAM 4 I/O20– I/O23 64K x 4 SRAM 4 I/O28– I/O31 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 I/OA94 I/O5 I/O6 I/O7 WE A14 CS1 CS3 NC GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND 1 23 45 67 89 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 CS4 NC OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-05270 Rev. Revised March 15, 2002 1 page Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[6] tWC ADDRESS tSCS CS WE DATA IN DATA OUT tAW tSA DATA UNDEFINED tPWE tHA tSD tHD DATA VALID tHZWE tLZWE HIGH IMPEDANCE CYM1831 Write Cycle No. 2 (CS Controlled)[6, 10] ADDRESS CS tSA WE tWC tAW DATA IN DATA OUT DATA UNDEFINED tSCS tPWE tHA tSD tHD DATA VALID tHZWE HIGH IMPEDANCE Note: 10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Truth Table CSN WE OE Inputs/Outputs Mode H X X High Z Deselect/Power-Down L H L Data Out Read L L X Data In Write L H H High Z Deselect Document #: 38-05270 Rev. Page 5 of 8 5 Page

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Número de pieza	Descripción	Fabricantes
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