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PDF 100301SC Data sheet ( Hoja de datos )
| Número de pieza | 100301SC | |
| Descripción | Low Power Triple 5-Input OR/NOR Gate | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1989
Revised August 2000
100301
Low Power Triple 5-Input OR/NOR Gate
General Description
The 100301 is a monolithic triple 5-input OR/NOR gate. All
inputs have 50 kΩ pull-down resistors and all outputs are
buffered.
Features
s 23% power reduction of the 100101
s 2000V ESD protection
s Pin/function compatible with 100101
s Voltage compensated operating range = −4.2V to −5.7V
s Available to industrial grade temperature range
(PLCC package only)
Ordering Code:
Order Number Package Number
Package Description
100301SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100301PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100301QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100301QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names
Dna, Dnb, Dnc
Oa, Ob, Oc
Oa, Ob, Oc
Description
Data Inputs
Data Outputs
Complementary Data Outputs
© 2000 Fairchild Semiconductor Corporation DS010579
28-Pin PLCC
www.fairchildsemi.com
1 page  
Test Circuitry
Notes:
VCC, VCCA = +2V, VEE = −2.5V
L1 and L2 = equal length 50Ω impedance lines
RT = 50Ω terminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ω to GND
CL = Fixture and stray capacitance ≤ 3 pF
Switching Waveforms
FIGURE 1. AC Test Circuit
FIGURE 2. Propagation Delay and Transition Times
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 100301SC.PDF ] | |
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