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LTC690IN8 の電気的特性と機能

LTC690IN8のメーカーはLinear Technologyです、この部品の機能は「Microprocessor Supervisory Circuits」です。


製品の詳細 ( Datasheet PDF )

部品番号 LTC690IN8
部品説明 Microprocessor Supervisory Circuits
メーカ Linear Technology
ロゴ Linear Technology ロゴ 




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LTC690IN8 Datasheet, LTC690IN8 PDF,ピン配置, 機能
FEATURES
s UL Recognized ® File # E145770
s Guaranteed Reset Assertion at VCC = 1V
s 1.5mA Maximum Supply Current
s Fast (35ns Max) Onboard Gating of RAM Chip
Enable Signals
s SO-8 and S16 Packaging
s 4.65V Precision Voltage Monitor
s Power OK/Reset Time Delay: 50ms, 200ms
or Adjustable
s Minimum External Component Count
s 1µA Maximum Standby Current
s Voltage Monitor for Power-Fail
or Low-Battery Warning
s Thermal Limiting
s Performance Specified Over Temperature
s Superior Upgrade for MAX690 Family
U
APPLICATIO S
s Critical µP Power Monitoring
s Intelligent Instruments
s Battery-Powered Computers and Controllers
s Automotive Systems
LTC690/LTC691
LTC694/LTC695
Microprocessor
Supervisory Circuits
DESCRIPTIO
The LTC®690 family provides complete power supply
monitoring and battery control functions for microproces-
sor reset, battery back-up, CMOS RAM write protection,
power failure warning and watchdog timing. A precise
internal voltage reference and comparator circuit monitor
the power supply line. When an out-of-tolerance condition
occurs, the reset outputs are forced to active states and the
chip enable output unconditionally write-protects external
memory. In addition, the RESET output is guaranteed to
remain logic low even with VCC as low as 1V.
The LTC690 family powers the active CMOS RAMs with a
charge pumped NMOS power switch to achieve low drop-
out and low supply current. When primary power is lost,
auxiliary power, connected to the battery input pin, powers
the RAMs in standby through an efficient PMOS switch.
For an early warning of impending power failure, the
LTC690 family provides an internal comparator with a
user-defined threshold. An internal watchdog timer is also
available, which forces the reset pins to active states when
the watchdog input is not toggled prior to a preset time-out
period.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
VIN 7.5V
+
10µF
LT ®1086-5
VIN VOUT
ADJ
5V
+
100µF
51k
10k
0.1µF
3V
VCC VOUT
LTC690/LTC691
LTC694/LTC695
VBATT
RESET
PFO
PFI GND WDI
0.1µF
MICROPROCESSOR RESET, BATTERY BACK-UP, POWER FAILURE
WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR MICROPROCESSOR SYSTEMS
0.1µF
POWER TO µP
CMOS RAM POWER
µP
SYSTEM
µP RESET
µP NMI
I/O LINE
100
690 TA01
RESET Output Voltage vs
Supply Voltage
5
TA = 25°C
EXTERNAL PULL-UP = 10µA
4 VBATT = 0V
3
2
1
0
01 2 345
SUPPLY VOLTAGE (V)
690 TA02
1

1 Page





LTC690IN8 pdf, ピン配列
LTC690/LTC691
LTC694/LTC695
ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
Battery Back-Up Switching
Operating Voltage Range
VOUT Output Voltage
CONDITONS
VCC
VBATT
IOUT = 1mA
VOUT in Battery Back-Up Mode
Supply Current (Exclude IOUT)
IOUT = 50mA
IOUT = 250µA, VCC < VBATT
IOUT 50mA
Supply Current in Battery Back-Up Mode
VCC = 0V, VBATT = 2.8V
Battery Standby Current (+ = Discharge, – = Charge) 5.5 > VCC > VBATT + 0.2V
Battery Switchover Threshold, VCC – VBATT
Battery Switchover Hysteresis
BATT ON Output Voltage (Note 4)
BATT ON Output Short-Circuit Current (Note 4)
Reset and Watchdog Timer
Reset Voltage Threshold
Reset Threshold Hysteresis
Reset Active Time (LTC690/91) (Note 5)
Power Up
Power Down
ISINK = 3.2mA
BATT ON = VOUT Sink Current
BATT ON = 0V Source Current
LTC690M
OSC SEL HIGH, VCC = 5V
Reset Active Time (LTC694/95) (Note 5)
OSC SEL HIGH, VCC = 5V
Watchdog Time-Out Period, Internal Oscillator
Long Period, VCC = 5V
Short Period, VCC = 5V
Watchdog Time-Out Period, External Clock (Note 6)
Reset Active Time PSRR
Watchdog Time-Out Period PSRR, Internal OSC
Minimum WDI Input Pulse Width
RESET Output Voltage at VCC = 1V
RESET and LOW LINE Output Voltage (Note 4)
RESET and WDO Output Voltage (Note 4)
Long Period
Short Period
VIL = 0.4V, VIH = 3.5V
ISINK = 10µA, VCC = 1V
ISINK = 1.6mA, VCC = 4.25V
ISOURCE = 1µA, VCC = 5V
ISINK = 1.6mA, VCC = 5V
ISOURCE = 1µA, VCC = 4.25V
MIN TYP
4.75
2.00
VCC – 0.05
q VCC – 0.10
VCC – 0.50
VBATT – 0.1
q
q
– 0.1
q –1.0
VCC – 0.005
VCC – 0.005
VCC – 0.250
VBATT – 0.02
0.6
0.6
0.04
0.04
70
50
20
35
0.5 1
q 4.5
q 4.4
40
q 35
160
q 140
1.2
q 1.0
80
q 70
4032
960
q 200
3.5
3.5
4.65
4.65
40
50
50
200
200
1.6
1.6
100
100
1
1
4
MAX UNITS
5.50
4.25
1.5
2.5
1
5
+ 0.02
+ 0.10
0.4
25
V
V
V
V
V
V
mA
mA
µA
µA
µA
µA
mV
mV
mV
V
m
µA
4.75 V
4.75 V
mV
60 ms
70 ms
240 ms
280 ms
2.00 sec
2.25 sec
120 ms
140 ms
4097 Clock
1025 Cycles
ms/V
ms/V
ns
200 mV
0.4 V
V
0.4 V
V
3


3Pages


LTC690IN8 電子部品, 半導体
LTC690/LTC691
LTC694/LTC695
PI FU CTIO S
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When VCC is lower than VBATT, C3 is shut down and
PFO is forced low.
RESET: Logic Output for µP Reset Control. Whenever VCC
falls below either the reset voltage threshold (4.65V,
typically) or VBATT, RESET goes active low. After VCC
returns to 5V, reset pulse generator forces RESET to
remain active low for a minimum of 35ms for the LTC690
/LTC691 (140ms for the LTC694/LTC695). When the
watchdog timer is enabled but not serviced prior to a
preset time-out period, reset pulse generator also forces
RESET to active low for a minimum of 35ms for the
LTC690/LTC691 (140ms for the LTC694/5) for every
preset time-out period (see Figure 11). The reset active
time is adjustable on the LTC691/LTC695. An external
push-button reset can be used in connection with the
RESET output. See Push-Button Reset in Applications
Information section.
RESET: RESET is an active high logic ouput. It is the
inverse of RESET.
LOW LINE: Logic Output from Comparator C1. LOW LINE
indicates a low line condition at the VCC input. When VCC
falls below the reset voltage threshold (4.65V typically),
LOW LINE goes low. As soon as VCC rises above the reset
voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when VCC drops below VBATT (see
Table 1).
WDI: Watchdog Input, WDI, is a three level input. Driving
WDI either high or low for longer than the watchdog time-
out period, forces both RESET and WDO low. Floating WDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).
WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
time-out period, WDO goes low. WDO is set high whenever
there is a transition on the WDI pin, or LOW LINE goes low.
The watchdog timer can be disabled by floating WDI (see
Figure 11).
CE IN: Logic input to the Chip Enable gating circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.
CE OUT: Logic Output on the Chip Enable Gating Circuit.
When VCC is above the reset voltage threshold, CE OUT is
a buffered replica of CE IN. When VCC is below the reset
voltage threshold CE OUT is forced high (see Figure 5).
OSC SEL: Oscillator Selection Input. When OSC SEL is
high or floating, the internal oscillator sets the reset active
time and watchdog time-out period. Forcing OSC SEL low,
allows OSC IN be driven from an external clock signal or
external capacitor be connected between OSC IN and
GND.
OSC IN: Oscillator Input. OSC IN can be driven by an
external clock signal or external capacitor can be connected
between OSC IN and GND when OSC SEL is forced low. In
this configuration the nominal reset active time and
watchdog time-out period are determined by the number
of clocks or set by the formula (see Applications Information
section). When OSC SEL is high or floating, the internal
oscillator is enabled and the reset active time is fixed at
50ms typical for the LTC691 and 200ms typical for the
LTC695. OSC IN selects between the 1.6 seconds and
100ms typical watchdog time-out periods. In both cases,
the time-out period immediately after a reset is 1.6 seconds
typical.
6

6 Page



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部品番号部品説明メーカ
LTC690IN8

Microprocessor Supervisory Circuits

Linear Technology
Linear Technology


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