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PDF LTC3414 Data sheet ( Hoja de datos )
| Número de pieza | LTC3414 | |
| Descripción | Monolithic Synchronous Step-Down Regulator | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC3414
4A, 4MHz, Monolithic
Synchronous Step-Down Regulator
FEATURES
DESCRIPTIO
■ High Efficiency: Up to 95%
■ 4A Output Current
■ Low Quiescent Current: 64μA
■ Low RDS(ON) Internal Switch: 67mΩ
■ Programmable Frequency: 300KHz to 4MHz
■ 2.25V to 5.5V Input Voltage Range
■ ±2% Output Voltage Accuracy
■ 0.8V Reference Allows Low Output Voltage
■ Selectable Forced Continuous/Burst Mode® Operation
with Adjustable Burst Clamp
■ Synchronizable Switching Frequency
■ Low Dropout Operation: 100% Duty Cycle
■ Power Good Output Voltage Monitor
■ Overtemperature Protected
■ Available in 20-Lead Exposed TSSOP Package
U
APPLICATIO S
■ Point-of-Load Regulation
■ Notebook Computers
■ Portable Instruments
■ Distributed Power Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, Including 5481178, 6580258, 6304066, 6127815, 6498466,
6611131, 6724174
The LTC®3414 is a high efficiency monolithic synchro-
nous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.25V to 5.5V and provides a
regulated output voltage from 0.8V to 5V while delivering
up to 4A of output current. The internal synchronous
power switch with 67mΩ on-resistance increases effi-
ciency and eliminates the need for an external Schottky
diode. Switching frequency is set by an external resistor or
can be synchronized to an external clock. 100% duty cycle
provides low dropout operation extending battery life in
portable systems. OPTI-LOOP® compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.
The LTC3414 can be configured for either Burst Mode
operation or forced continuous operation. Forced continu-
ous operation reduces noise and RF interference while
Burst Mode operation provides high efficiency by reduc-
ing gate charge losses at light loads. In Burst Mode
operation, external control of the burst clamp level allows
the output voltage ripple to be adjusted according to the
requirements of the application.
TYPICAL APPLICATIO
VIN
2.7V TO 5.5V
22μF
2.2M
294k
PVIN SVIN
RT PGOOD
LTC3414
SW
1000pF
470pF
RITH*
RUN/SS PGND
ITH SGND
SYNC/MODE VFB
75k 110k
0.47μH
VOUT
2.5V AT 4A
COUT*
392k
3414 F01a
*Burst Mode OPERATION: COUT = 470μF SANYO POSCAP 4TPB470M, RITH = 20k
FORCED CONTINUOUS: COUT = (2) 100μF TDKC4532X5ROJ107M, RITH = 12.1k
Figure 1. 2.5V/4A Step-Down Regulator
LTC3414 Efficiency Curve
100
95 Burst Mode OPERATION
90
85
80 FORCED
CONTINUOUS
75
70
65
60
55
50
0.001
0.01 0.1
1.0
LOAD CURRENT (A)
10
3414 F01b
3414fb
1
1 page  
TYPICAL PERFOR A CE CHARACTERISTICS
Load Step Transient Burst Mode
Operation
OUTPUT
VOLTAGE
100mV/DIV
INDUCTOR
CURRENT
2A/DIV
20μs/DIV
VIN = 3.3V, VOUT = 2.5V
LOAD STEP = 250mA TO 4A
3414 G18
Start-Up Transient
VRUN
OUTPUT
VOLTAGE
INDUCTOR
CURRENT
2A/DIV
1ms/DIV
VIN = 3.3V, VOUT = 2.5V
LOAD = 4A
LTC3414
3414 G19
PI FU CTIO S
PGND (Pins 1, 10, 11, 20): Power Ground. Connect this
pin closely to the (–) terminal of CIN and COUT.
RT (Pin 2): Oscillator Resistor Input. Connecting a resistor
to ground from this pin sets the switching frequency.
SYNC/MODE (Pin 3): Mode Select and External Clock
Synchronization Input. To select Forced Continuous, tie to
SVIN. Connecting this pin to a voltage between 0V and 1V
selects Burst Mode operation with the burst clamp set to
the pin voltage.
RUN/SS (Pin 4): Run Control and Soft-Start Input. Forcing
this pin below 0.5V shuts down the LTC3414. In shutdown
all functions are disabled. Less than 1μA of supply current
is consumed. A capacitor to ground from this pin sets the
ramp time to full output current.
SGND (Pin 5):Signal Ground. All small signal components
and compensation components should connect to this
ground, which in turn connects to PGND at one point.
NC (Pin 6): Open. No internal connection.
PVIN (Pins 7, 14): Power Input Supply. Decouple this pin
to PGND with a capacitor.
SW (Pins 8, 9, 12, 13): Switch Node Connection to
Inductor. This pin connects to the drains of the internal
main and synchronous power MOSFET switches.
NC (Pin 15): Open. No internal connection.
SVIN (Pin 16): Signal Input Supply. Decouple this pin to
SGND with a capacitor.
PGOOD (Pin 17): Power Good Output. Open drain logic
output that is pulled to ground when the output voltage is
not within ±7.5% of regulation point.
ITH (Pin 18): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.2V to
1.4V with 0.4V corresponding to the zero-sense voltage
(zero current).
VFB (Pin 19): Feedback Pin. Receives the feedback voltage
from a resistive divider connected across the output.
Exposed Pad (Pin 21): Should be connected to SGND and
soldered to the PCB.
3414fb
5
5 Page 
LTC3414
APPLICATIO S I FOR ATIO
The VIN quiescent current loss dominates the efficiency
loss at very low load currents whereas the I2R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The VIN quiescent current is due to two components:
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current out
of VIN that is typically larger than the DC bias current. In
continuous mode, IGATECHG = f(QT + QB) where QT and QB
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to VIN; thus, their effects will be more pro-
nounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In con-
tinuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. To obtain I2R losses, simply add RSW to RL and
multiply the result by the square of the average output
current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3414 does not dissipate
much heat due to its high efficiency.
However, in applications where the LTC3414 is running at
high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
150°C, both power switches will be turned off and the SW
node will become high impedance.
To avoid the LTC3414 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
tr = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature. For the 20-lead exposed TSSOP
package, the θJA is 38°C/W.
The junction temperature, TJ, is given by:
TJ = TA + tr
where TA is the ambient temperature.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (RDS(ON)).
To maximize the thermal performance of the LTC3414, the
exposed pad should be soldered to a ground plane.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current.
When a load step occurs, VOUT immediately shifts by an
amount equal to ΔILOAD(ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error signal used by
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The ITH pin external components and output capaci-
tor shown in Figure 1 will provide adequate compensation
for most applications.
3414fb
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LTC3414.PDF ] | |
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