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MJ-80C32E-30-E の電気的特性と機能

MJ-80C32E-30-EのメーカーはATMEL Corporationです、この部品の機能は「Rad. Tolerant 8-bit ROMless Microcontroller」です。


製品の詳細 ( Datasheet PDF )

部品番号 MJ-80C32E-30-E
部品説明 Rad. Tolerant 8-bit ROMless Microcontroller
メーカ ATMEL Corporation
ロゴ ATMEL Corporation ロゴ 




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MJ-80C32E-30-E Datasheet, MJ-80C32E-30-E PDF,ピン配置, 機能
Features
8032 Pin and Instruction Compatible
Four 8-bit I/O Ports
Three 16-bit Timer/Counters
256 bytes RAM
Full-duplex UART
Asynchronous Port Reset
6 Sources, 2 Level Interrupt Structure
64 Kbytes Program Memory Space
64 Kbytes Data Memory Space
Power Control Modes
Idle Mode
Power-down Mode
On-chip Oscillator
Operating Frequency: 30 MHz
Power Supply: 4.5V to 5.5V
Temperature Range: Military (-55oC to 125oC)
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2
Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019
Packages: Side Brazed 40-pin, MQFPJ 44-pin
QML Q and V with SMD 5962-00518
SCC C an B with Specification SCC9521002
Rad. Tolerant
8-bit ROMless
Microcontroller
80C32E
Description
The 80C32E is a radiation tolerant ROMless version of the 80C52 single chip 8-bit
microcontroller.
The 80C32E retains all the features of the 80C32 with 256 bytes of internal RAM, a 6-
source, 2-level interrupt system, an on-chip oscillator and three 16-bit timer/counters.
The fully static design of the 80C32E reduces system power consumption by bringing
the clock frequency down to any value, even DC, without loss of data.
The 80C32E has 2 software-selectable modes of reduced activity for further reduction
in power consumption. In the idle mode the CPU is frozen while the timers, the serial
port and the interrupt system are still operating. In the power-down mode the RAM is
saved and all other functions are inoperative.
Rev. 4149M–AERO–06/04
1

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MJ-80C32E-30-E pdf, ピン配列
Pin Description
80C32E
Mnemonic
VSS
VCC
P0.0-P0.7
P1.0-P1.7
P2.0-P2.7
P3.0-P3.7
RST
Type Name and Function
I Ground: 0V reference
I
Power Supply: This is the power supply voltage for normal, idle and
power-down operation
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high impedance inputs.
Port 0 pins must be polarized to Vcc or Vss in order to prevent any
I/O parasitic current consumption. Port 0 is also the multiplexed low-order
address and data bus during access to external program and data
memory. In this application, it uses strong internal pull-up when emitting
1s.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
I/O pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 1 pins that are externally
pulled low will source current because of the internal pull-ups.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 2 pins that are externally
pulled low will source current because of the internal pull-ups. Port 2
I/O emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR).In this application, it uses strong internal
pull-ups emitting 1s. During accesses to external data memory that use
8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, Port 3 pins that are externally
pulled low will source current because of the internal pull-ups. Port 3 also
serves the special features of the 80C51 family, as listed below.
I RXD (P3.0): Serial input port
O TXD (P3.1): Serial output port
I INT0 (P3.2): External interrupt 0
I INT1 (P3.3): External interrupt 1
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
Reset: A high on this pin for two machine cycles while the oscillator is
I running, resets the device. An internal diffused resistor to VSS permits a
power-on reset using only an external capacitor to VCC.
4149M–AERO–06/04
3


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MJ-80C32E-30-E 電子部品, 半導体
Idle Mode
An instruction that sets PCON.0 causes that to be the last instruction executed before
going into Idle mode. In Idle mode, the internal clock signal is gated off to the CPU, but
not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its
entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM
and all other registers maintain their data during Idle. The port pins hold the logical
states they had at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be ser-
viced, and following RETI the next instruction to be executed will be the one following
the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred dur-
ing normal operation or during an Idle. For example, an instruction that activates Idle
can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt
service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode
To save maximum power, a power-down mode can be invoked by software.
In power-down mode, the oscillator is stopped and the instruction that invoked power-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from power-
down. To properly terminate power-down, the reset or external interrupt should not be
executed before VCC is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that,
interrupt must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 1. When both interrupts are enabled, the oscillator restarts as soon as
one of the two inputs is held low and Power-down exit will be completed when the first
input will be released. In this case the higher priority interrupt service routine is executed
Once the interrupt is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put 80C32E into power-down mode.
Figure 1. Power-down Exit Waveform
INT0
INT1
XTAL1
Active phase
Power-down phase Oscillator restart phase
Active phase
Exit from power-down by reset redefines all the SFRs, exit from power-down by external
interrupt does no affect the SFRs.
6 80C32E
4149M–AERO–06/04

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部品番号部品説明メーカ
MJ-80C32E-30-E

Rad. Tolerant 8-bit ROMless Microcontroller

ATMEL Corporation
ATMEL Corporation


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