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PDF AMPAL22V10 Data sheet ( Hoja de datos )
| Número de pieza | AMPAL22V10 | |
| Descripción | PAL22V10 Family/ AmPAL22V10/A 24-Pin TTL Versatile PAL Device | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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FINAL
COM’L: -7/10/15
PAL22V10 Family, AmPAL22V10/A
24-Pin TTL Versatile PAL Device
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
s As fast as 7.5-ns propagation delay and
91 MHz fMAX (external)
s 10 Macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
s Varied product term distribution allows up to
16 product terms per output for complex
functions
GENERAL DESCRIPTION
The PAL22V10 provides user-programmable logic for
replacing conventional SSI/MSI gates and flip-flops at a
reduced chip count.
The PAL22V10 device implements the familiar Boolean
logic transfer function, the sum of products. The PAL de-
vice is a programmable AND array driving a fixed OR
array. The AND array is programmed to create custom
product terms, while the OR array sums selected terms
at the outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to 16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
BLOCK DIAGRAM
CLK/I0
1
s Global asynchronous reset and synchronous
preset for initialization
s Power-up reset for initialization and register
preload for testability
s Extensive third-party software and programmer
support through FusionPLD partners
s 24-Pin SKINNYDIP, 24-pin Flatpack and
28-pin PLCC and LCC packages save space
grammed as registered or combinatorial, and active
high or active low. The output configuration is
determined by two fuses controlling two multiplexers in
each macrocell.
AMD’s FusionPLD program allows PAL22V10 designs
to be implemented using a wide variety of popular indus-
try-standard design tools. By working closely with the
FusionPLD partners, AMD certifies that the tools pro-
vide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
I1 - I11
11
Programmable
AND Array
(44 x 132)
8
10
12
14 16
16
14 12 10
8
RESET
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
PRESET
I/O0 I/O1
I/O2 I/O3 I/O4
Publication# 16559 Rev. C Amendment /0
Issue Date: February 1996
I/O5 I/O6 I/O7 I/O8 I/O9 16559C-1
2-197
1 page  
Registered Output Configuration
Each macrocell of the PAL22V10 includes a D-type flip-
flop for data storage and synchronization. The flip-flop
is loaded on the LOW-to-HIGH transition of the clock in-
put. In the registered configuration (S1 = 0), the array
feedback is from Q of the flip-flop.
S0 = 0
AR S1 = 0
DQ
CLK Q
SP
AMD
Combinatorial I/O Configuration
Any macrocell can be configured as combinatorial by
selecting the multiplexer path that bypasses the flip-flop
(S1 = 1). In the combinatorial configuration the feedback
is from the pin.
S0 = 0
S1 = 1
Registered/Active Low
Combinatorial/Active Low
AR
DQ
CLK Q
SP
S0 = 1
S1 = 0
S0 = 1
S1 = 1
Registered/Active High
Combinatorial/Active High
Figure 2. Macrocell Configuration Options
16559C-5
Programmable Three-State Outputs
Each output has a three-state output buffer with three-
state control. A product term controls the buffer, allow-
ing enable and disable to be a function of any product of
device inputs or output feedback. The combinatorial
output provides a bidirectional I/O pin, and may be con-
figured as a dedicated input if the buffer is always dis-
abled.
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Selection is controlled by programmable bit S0 in the
output macrocell, and affects both registered and com-
binatorial outputs. Selection is automatic, based on the
design specification and pin definitions.
Preset/Reset
For initialization, the PAL22V10 has Preset and Reset
product terms. These terms are connected to all regis-
tered outputs. When the Synchronous Preset (SP)
product term is asserted high, the output registers will be
loaded with a HIGH on the next LOW-to-HIGH clock
transition. When the Asynchronous Reset (AR) product
term is asserted high, the output registers will be imme-
diately loaded with a LOW independent of the clock.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable
system initialization. Outputs of the PAL22V10 will de-
pend on the programmed output polarity. The VCC rise
must be monotonic and the reset delay time is 1000 ns
maximum.
PAL22V10 Family
2-201
5 Page 
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
Test Conditions
Typ Unit
CIN
COUT
Input Capacitance
Output Capacitance
VIN = 2.0 V
VOUT = 2.0 V
VCC = 5.0 V
TA = 25°C
f = 1 MHz
6
pF
5
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol Parameter Description
Min
(Note 3)
Max
Unit
tPD Input or Feedback to Combinatorial Output
1 10 ns
tS Setup Time from Input, Feedback or SP to Clock
7 ns
tH Hold Time
0 ns
tCO Clock to Output
1 7 ns
tAR Asynchronous Reset to Registered Output
15 ns
tARW
Asynchronous Reset Width
10 ns
tARR Asynchronous Reset Recovery Time
8 ns
tSPR Synchronous Preset Recovery Time
8 ns
tWL
Clock Width
tWH
LOW
HIGH
5 ns
5 ns
fMAX
Maximum
Frequency
(Note 4)
External Feedback
1/(tS + tCO)
Internal Feedback (fCNT) 1/(tS + tCF) (Note 5)
No Feedback
1/(tWH + tWL)
71
80
100
MHz
MHz
MHz
tEA Input to Output Enable Using Product Term Control
11 ns
tER Input to Output Disable Using Product Term Control
9 ns
Notes:
2. See Switching Test Circuit for test conditions.
3. Output delay minimums are measured under best-case conditions.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
PAL22V10-10 (Com’l)
2-207
11 Page | ||
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| PDF Descargar | [ Datasheet AMPAL22V10.PDF ] | |
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