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AT29C432-12 の電気的特性と機能

AT29C432-12のメーカーはATMEL Corporationです、この部品の機能は「4 Megabit 5-volt Flash with 256K E2PROM Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 AT29C432-12
部品説明 4 Megabit 5-volt Flash with 256K E2PROM Memory
メーカ ATMEL Corporation
ロゴ ATMEL Corporation ロゴ 




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AT29C432-12 Datasheet, AT29C432-12 PDF,ピン配置, 機能
Features
ConcurrentFlashMemory
Unique Architecture Allows the Flash Array
To Be Read During the E2PROM Write Cycle
4 Megabit 5-volt Flash
Configured as a 512K x 8 Memory Array
120 ns Read Access Time
Sector Program Operation
Single Cycle Reprogram (No Erase Necessary)
2048 Sectors, 256-Bytes Wide
10 ms Sector Rewrite
JEDEC Standard Software Data Protection
256K bit Full Feature E2PROM
Configured as a 32K x 8 Memory Array
Byte or Page (16 bytes) Write Capability
Write Cycle Time: 10 ms
JEDEC Standard Software Data Protection
Pinout Similar to 32-Pin 4 Mb Flash
•• Data Memory Endurance: 10,000 cycles
Description
The AT29C432 is a CMOS memory specifically designed for applications requiring
both a high density nonvolatile program memory and a smaller nonvolatile data mem-
ory. The AT29C432 provides this in the form of a 4 megabit Flash array integrated
with a 256K bit full featured E2PROM array on the same device. A unique feature of
this device is its concurrent read while writing capability. This provides the host sys-
tem read access to the Flash program memory during the write cycle time of the
E2PROM.
The two memory arrays share all I/O lines, Address lines and OE and WE inputs.
Each memory array has its own Chip Enable input: CEF for the Flash array and CEE
for the E2PROM array.
Additionally, Software Data Protection has been independently implemented for both
arrays and is always enabled. The AT29C432 has a pinout similar to the AT29C040A
Flash memory. A system designer using a Flash memory for program storage and
another smaller, non volatile memory for data storage can easily replace both memo-
ries with the AT29C432.
4 Megabit
5-volt Flash with
256K E2PROM
Memory
AT29C432
ConcurrentFlash
Preliminary
Pin Configurations
Pin Name Function
A0 - A18 Addresses
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
CEE
Chip Enable E2PROM
CEF
Chip Enable Flash
NC No Connect
TSOP
Type 1

1 Page





AT29C432-12 pdf, ピン配列
AT29C432
Device Operation (Continued)
high transition, the load period will end and the internal
programming period will start. The sector address must
be valid during each high to low transition of WE (or CEF).
The bytes may be loaded in any order; sequential loading
is not required. Once a programming operation has been
initiated, and for the duration of tWCF, a read operation will
effectively be a data polling operation.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the Flash memory
array in the following ways: (a) VCC sense—if VCC is be-
low 3.8V (typical), the program function is inhibited. (b)
VCC power on delay—once VCC has reached the VCC
sense level, the device will automatically time out 10 ms
(typical) before programming. (c) Program inhibit—hold-
ing any one of OE low, CEF high or WE high inhibits pro-
gram cycles. (d) Noise filter—pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
DATA POLLING: A maximum amount of time for pro-
gram and write operations is specified; the actual time is
frequently faster than the specification. In order to take ad-
vantage of the faster typical times, the Flash memory ar-
ray features DATA polling to indicate the end of a program
cycle. During a program cycle an attempted read of the
last byte loaded will result in the complement of the loaded
data on I/O7. Once the program cycle has been com-
pleted, true data is valid on all outputs and the next cycle
may begin. DATA polling may begin at any time during the
program cycle.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product. In addition, users may wish to use the
software product identification mode to identify the part
(i.e. using the device code), and have the system software
use the appropriate sector size for program operations.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
E2PROM Memory Array
READ: The E2PROM memory array is read like a Static
RAM. When CEE and OE are low and WE and CEF are
high, the data stored at the memory location determined
by the address inputs is asserted on the I/O’s.
WRITE: The E2PROM memory array may be written in
either a single byte write or page write operation. Be-
cause software data protection is always enabled both
write operations must be preceded by the three byte write
command sequence. This sequence should then immedi-
ately be followed by one to sixteen bytes of data. After the
last byte has been written, the AT29C432 will automat-
ically time itself to completion of the internal write cycle.
The write cycle is initiated by both WE and CEE going low;
the address is latched by the falling edge of WE or CEE
(whichever occurs last) and the data is latched by the ris-
ing edge of WE or CEE (whichever occurs first). All write
operations (byte or page) must conform to the page write
limits as shown in the timing diagram for E2PROM write
operations. All bytes during a page write operation must
reside on the same page as defined by the state of the A4
- A14 inputs. For each WE high to low transition during
the page write operation, A4 - A14 must be the same.
The A0 - A3 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in
any order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
During the internal write operation (tWCE) attempts to read
the E2PROM will be equivalent to DATA polling opera-
tions; however, attempts to read the Flash array will return
valid data.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the E2PROM
memory array in the following ways: (a) VCC sense—if
VCC is below 3.8V (typical), the program function is inhib-
ited. (b) VCC power on delay—once VCC has reached the
VCC sense level, the device will automatically time out 10
ms (typical) before programming. (c) Program inhibit—
holding any one of OE low, CEE high or WE high inhibits
program cycles. (d) Noise filter—pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
DATA POLLING: A maximum amount of time for pro-
gram and write operations is specified; the actual time is
frequently faster than the specification. In order to take
advantage of the faster typical times, the E2PROM mem-
ory array features DATA polling to indicate the end of a
program cycle. During a program cycle an attempted read
of the last byte loaded will result in the complement of the
loaded data on I/O7. Once the program cycle has been
completed, true data is valid on all outputs and the next
cycle may begin. DATA polling may begin at any time dur-
ing the program cycle.
(continued)
3


3Pages


AT29C432-12 電子部品, 半導体
AC Read Characteristics
Symbol
tCED
tACC
tCE (1)
tOE (2)
tDF (3, 4)
tOH
Parameter
CEE to CEF Active Delay (or CEF to
CEE Active Delay)
Address to Output Delay
CEE (or CEF) to Output Delay
OE to Output Delay
CE or OE to Output Float
Output Hold from OE, CEE or CEF or
Address change
AT29C432-12
Min Max
100
120
120
0 50
0 30
0
AC Read Waveforms (1, 2, 3, 4)
AT29C432-15
Min Max
100
150
0 150
0 70
0 40
0
Units
ns
ns
ns
ns
ns
ns
Notes: 1. CEF (CEE) may be delayed up to tACC - tCE after the
address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling
edge of CEF (CEE) without impact on tCE or by
tACC - tOE after an address change without impact on
tACC.
3. tDF is specified from OE or CEF (CEE) whichever occurs first
(CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
6 AT29C432

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
AT29C432-12

4 Megabit 5-volt Flash with 256K E2PROM Memory

ATMEL Corporation
ATMEL Corporation
AT29C432-12TC

4 Megabit 5-volt Flash with 256K E2PROM Memory

ATMEL Corporation
ATMEL Corporation
AT29C432-12TI

4 Megabit 5-volt Flash with 256K E2PROM Memory

ATMEL Corporation
ATMEL Corporation
AT29C432-15

4 Megabit 5-volt Flash with 256K E2PROM Memory

ATMEL Corporation
ATMEL Corporation


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