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PDF CY37032P44-154AC Data sheet ( Hoja de datos )
| Número de pieza | CY37032P44-154AC | |
| Descripción | 5V/ 3.3V/ ISR High-Performance CPLDs | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
General Description
• In-System Reprogrammable™ (ISR™) CMOS CPLDs
— JTAG interface for reconfigurability
— Design changes do not cause pinout changes
— Design changes do not cause timing changes
• High density
— 32 to 512 macrocells
— 32 to 264 I/O pins
— Five dedicated inputs including four clock pins
• Simple timing model
— No fanout delays
— No expander delays
— No dedicated vs. I/O pin delays
— No additional delay through PIM
— No penalty for using full 16 product terms
— No delay for steering or sharing product terms
• 3.3V and 5V versions
• PCI-compatible[1]
• Programmable bus-hold capabilities on all I/Os
• Intelligent product term allocator provides:
— 0 to 16 product terms to any macrocell
— Product term steering on an individual basis
The Ultra37000™ family of CMOS CPLDs provides a range of
high-density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to
bring the flexibility, ease of use, and performance of the 22V10
to high-density CPLDs. The architecture is based on a number
of logic blocks that are connected by a Programmable Inter-
connect Matrix (PIM). Each logic block features its own
product term array, product term allocator, and 16 macrocells.
The PIM distributes signals from the logic block outputs and all
input pins to the logic block inputs.
All of the Ultra37000 devices are electrically erasable and In-
System Reprogrammable (ISR), which simplifies both design
and manufacturing flows, thereby reducing costs. The ISR
feature provides the ability to reconfigure the devices without
having design changes cause pinout or timing changes. The
Cypress ISR function is implemented through a JTAG-
compliant serial interface. Data is shifted in and out through
the TDI and TDO pins, respectively. Because of the superior
routability and simple timing model of the Ultra37000 devices,
ISR allows users to change existing logic designs while simul-
taneously fixing pinout assignments and maintaining system
performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting the electrical and timing requirements. The
Ultra37000 family features user programmable bus-hold
capabilities on all I/Os.
— Product term sharing among local macrocells
• Flexible clocking
— Four synchronous clocks per device
— Product term clocking
— Clock polarity control per logic block
• Consistent package/pinout offering across all densities
— Simplifies design migration
Ultra37000 5.0V Devices
The Ultra37000 devices operate with a 5V supply and can
support 5V or 3.3V I/O levels. VCCO connections provide the
capability of interfacing to either a 5V or 3.3V bus. By
connecting the VCCO pins to 5V the user insures 5V TTL levels
on the outputs. If VCCO is connected to 3.3V the output levels
meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.
These devices require 5V ISR programming.
— Same pinout for 3.3V and 5.0V devices
Ultra37000V 3.3V Devices
• Packages
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,
Devices operating with a 3.3V supply require 3.3V on all VCCO
pins, reducing the device’s power consumption. These
BGA, and Fine-Pitch BGA packages
devices support 3.3V JEDEC standard CMOS output levels,
and are 5V-tolerant. These devices allow 3.3V ISR
programming.
Note:
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03007 Rev. *C
Revised July 7, 2003
1 page  
Ultra37000 CPLD Family
The buried macrocell also supports input register capability.
The buried macrocell can be configured to act as an input
register (D-type or latch) whose input comes from the I/O pin
associated with the neighboring macrocell. The output of all
buried macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macrocell
Figure 2 illustrates the architecture of the I/O macrocell. The
I/O macrocell supports the same functions as the buried
macrocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or active HIGH signals. This has the added advantage
of allowing significant logic reduction to occur in many appli-
cations.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in bus-
interface applications. Bus-hold additionally allows unused
device pins to remain unconnected on the board, which is
particularly useful during prototyping as designers can route
new signals to the device without cutting trace connections to
VCC or GND. For more information, see the application note
“Understanding Bus-Hold — A Feature of Cypress CPLDs.”
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high perfor-
mance the fast edge rate provides maximum system perfor-
mance.
Document #: 38-03007 Rev. *C
Page 5 of 62
5 Page 
Logic Block Diagrams (continued)
CY37256/CY37256V (256-lead BGA)
Clock/
Input Input
14
Ultra37000 CPLD Family
TDI
TCK
TMS
12 I/Os
I/O0−I/O11
12 I/Os
I/O12−I/O23
12 I/Os
I/O24−I/O35
12 I/Os
I/O36−I/O47
12 I/Os
I/O48−I/O59
12 I/Os
I/O60−I/O71
12 I/Os
I/O72−I/O83
12 I/Os
I/O84−I/O95
JTAG Tap
Controller
TDO
4
LOGIC
BLOCK
A
LOGIC
BLOCK
B
LOGIC
BLOCK
C
LOGIC
BLOCK
D
LOGIC
BLOCK
E
LOGIC
BLOCK
F
LOGIC
BLOCK
G
LOGIC
BLOCK
H
36
16
36
16
36
16
36
16
36
16
36
16
36
16
36
16
96
PIM
4
36
LOGIC
16 BLOCK
P
36
LOGIC
16 BLOCK
O
36
LOGIC
16 BLOCK
N
36
LOGIC
16 BLOCK
M
36 LOGIC
16 BLOCK
L
36
LOGIC
16 BLOCK
K
36
LOGIC
16 BLOCK
J
36
LOGIC
16 BLOCK
I
96
12 I/Os
I/O180−I/O191
12 I/Os
I/O168−I/O179
12 I/Os
I/O156−I/O167
12 I/Os
I/O144−I/O155
12 I/Os
I/O132−I/O143
12 I/Os
I/O120−I/O131
12 I/Os
I/O108−I/O119
12 I/Os
I/O96−I/O107
Document #: 38-03007 Rev. *C
Page 11 of 62
11 Page | ||
| Páginas | Total 62 Páginas | |
| PDF Descargar | [ Datasheet CY37032P44-154AC.PDF ] | |
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