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PDF CXP84540 Data sheet ( Hoja de datos )
| Número de pieza | CXP84540 | |
| Descripción | CMOS 8-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXP84540/84548
CMOS 8-bit Single Chip Microcomputer
Description
The CXP84540/84548 is a CMOS 8-bit micro-
computer integrating on a single chip an A/D converter,
serial interface, timer/counter, time-base timer, capture
timer/counter, PWM output and the like besides the
basic configurations of 8-bit CPU, ROM, RAM and I/O
port.
The CXP84540/84548 also provide a sleep/stop
functions that enable to execute the power-on reset
function or lower the power consumption.
80 pin QFP (Plastic) 80 pin LQFP (Plastic)
80 pin LFLGA (Plastic)
Features
• Wide range instruction system (213 instructions)
which covers various of data
— 16-bit arithmetic/multiplication and
division/Boolean bit operation instructions
• Minimum instruction cycle 143ns at 28MHz operation (4.5 to 5.5V)
200ns at 20kHz operation (3.0 to 5.5V)
• Incorporated ROM capacity 40K bytes (CXP84540)
48K bytes (CXP84548)
• Incorporated RAM capacity 1472 bytes
• Peripheral functions
— A/D converter
8 bits, 8 channels, successive approximation method
(Conversion time of 1.93µs / at 28MHz, 2.7µs / at 20MHz)
— Serial interface
Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes,
latch output function, MSB/LSB first selectable), 1 channel
8-bit clock syncronization, 1 channel
— Timer
8-bit timer
8-bit timer/counter
19-bit time-base timer
16-bit capture time/counter
— PWM output
8 bits, 2 channels
• Interruption
14 factors, 14 vectors, multi-interruption possible
• Standby mode
Sleep/Stop
• Package
80-pin plastic QFP/LQFP
80-pin plastic LFLGA
• Piggyback/evaluator
CXP84500
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96528B9X-PS
1 page  
Pin Assignment (Top View) 80-pin LFLGA package
CXP84540/84548
80 78 75 72 69 67 65 62
PF4 PF2 PG7 PG4 PG3 PG1 PI7
2 1 79 76 73 70 66 63
PF6 PF5 PF3 PF0 PG5 VDD PG0 PI5
PI4
61 60
PI3 PI2
5 3 4 77 74 71 68 64 59 58
PD1 PF7 PD0 PF1 PG6 NC PG2 PI6 PI1 PI0
768
57 56 55
PD3 PD2 PD4
9 10 11
PE5 PE4 PE3
54 53 52
PD5 PD6 PD7
12 13 14
PE2 PE1 PE0
51 50 49
PC0 PC1 PC2
PB7 PB6 PB5
15 16 17
PC3 PC4 PC5
48 46 47
PB4 PB2 PB3
18 19 24 28 31 34 37 44 43 45
PC6 PC7 PH4 RST VSS AVSS PA1 PB0 PA7 PB1
20 21 23 26 30 33 36 39 41 42
PH0 PH1 PH3 PH6 XTAL PE7 PA0 PA3 PA5 PA6
22 25 27 29 32 35 38 40
PH2 PH5 PH7 EXTAL PE6 AVREF PA2 PA4
Note) NC (Pin 71) is left open.
–5–
5 Page 
CXP84540/84548
Pin
PD0 to PD7
PF0 to PF7
PG0 to PG7
PI4 to PI7
28 pins
Port D
Port F
Port G
Port I
Circuit format
Pull-up resistor
"0" when reset
Ports D, F, G, I data
∗
Ports D, F, G, I direction
"0" when reset
Data bus
RD
Port H
IP
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
When reset
Hi-Z
PH0 to PH7
8 pins
Pull-up resistor
"0" when reset
Port H data
∗
Port H direction
"0" when reset
Data bus
RD (Port H)
Edge detection
Standby release
IP
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
Hi-Z
PI0/INT0
to
PI3/INT3
4 pins
Port I
Pull-up resistor
"0" when reset
Port I data
Data bus
Port I direction
"0" when reset
RD
INT0
INT1
INT2
INT3
∗
IP
Schmitt input
∗ Pull-up transistor
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)
Hi-Z
– 11 –
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet CXP84540.PDF ] | |
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