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HMA510883 の電気的特性と機能

HMA510883のメーカーはIntersil Corporationです、この部品の機能は「16 x 16-Bit CMOS Parallel Multiplier Accumulator」です。


製品の詳細 ( Datasheet PDF )

部品番号 HMA510883
部品説明 16 x 16-Bit CMOS Parallel Multiplier Accumulator
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HMA510883 Datasheet, HMA510883 PDF,ピン配置, 機能
HMA510/883
April 1997
16 x 16-Bit CMOS Parallel
Multiplier Accumulator
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 16 x 16-Bit Parallel Multiplication with Accumulation
to a 35-Bit Result
• High-Speed (55ns) Multiply Accumulate Time
• Low Power CMOS Operation
- ICCSB = 500µA Maximum
- ICCOP = 7.0mA Maximum at 1.0MHz
• HMA510/883 is Compatible with the CY7C510 and the
IDT7210
• Supports Two’s Complement or Unsigned Magnitude
Operations
• Three-State Outputs
Ordering Information
PART NUMBER
HMA510GM-55/883
HMA510GM-65/883
HMA510GM-75/883
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 68 Ld CPGA
-55 to 125 68 Ld CPGA
-55 to 125 68 Ld CPGA
PKG.
NO.
G68.B
G68.B
G68.B
Description
The HMA510/883 is a high speed, low power CMOS 16 x
16-bit parallel multiplier accumulator capable of operating at
55ns clocked multiply-accumulate cycles. The 16-bit X and Y
operands may be specified as either two’s complement or
unsigned magnitude format. Additional inputs are provided
for the accumulator functions which include: loading the
accumulator with the current product, adding or subtracting
the accumulator contents and the current product, and pre-
loading the Accumulator Registers from the external inputs.
All inputs and outputs are registered. The registers are all
positive edge triggered, and are latched on the rising edge of
the associated clock signal. The 35-bit Accumulator Output
Register is broken into three parts. The 16-bit least signifi-
cant product (LSP), the 16-bit most significant product
(MSP), and the 3-bit extended product (XTP) Registers. The
XTP and MSP Registers have dedicated output ports, while
the LSP Register shares the Y-inputs in a multiplexed fash-
ion. The entire 35-bit Accumulator Output Register may be
preloaded at any time through the use of the bidirectional
output ports and the preloaded control.
Block Diagram
X0-15
16
RND SUB Y0-15 P0-15
TC ACC
16
PRELOAD
CLKP
REGISTER
REGISTER
REGISTER
CLKY
CLKX
XTP REGISTER
MULTIPLIER ARRAY
35
ACCUMULATOR
MSP REGISTER LSP REGISTER
3 16
35
16
OEX
OEM
OEL
P32-34
P16-31
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-10
File Number 2807.2

1 Page





HMA510883 pdf, ピン配列
HMA510/883
Pin Descriptions (Continued)
NAME
TYPE
DESCRIPTION
SUB
I Subtract Control. When both SUB and ACC are HIGH, the Accumulator Register contents are sub-
tracted from the current product. When ACC is HIGH and SUB is LOW, the Accumulator Register
contents and the current product are summed. The SUB control input is latched on the rising edge of
CLKX or CLKY.
RND
I Round Control. When this control is HIGH, a one is added to the most significant bit of the LSP. When
LOW, the product is unchanged.
PREL
I Preload Control. When this control is HIGH, the three bidirectional ports may be used to preload the
Accumulator Registers. The three-state controls (OEX, OEM, OEL) must be HIGH, and the data will
be preloaded on the rising edge of CLKP. When this control is LOW, the Accumulator Registers func-
tion in a normal manner.
OEL
I Y-Input/LSP Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high
impedance state. This state is required for Y-data input or preloading the LSP Register. When OEL
is LOW, the port is enabled for LSP output.
OEM
I MSP Output Port Three-State Control. A LOW on this control line enables the port for output. When
OEM is HIGH, the output drivers are in the high impedance state.
This control must be HIGH for preloading the MSP Register.
OEX
I XTP Output Port Three-State Control. A LOW on this control line enables the port for output. When
OEX is HIGH, the output drivers are in the high impedance state. This control must be HIGH for pre-
loading the XTP Register.
CLKX
I X-Register Clock. The rising edge of this clock latches the X-Data Input Register along with the TC,
ACC, SUB and RND inputs.
CLKY
I Y-Register Clock. The rising edge of this clock latches the Y-Data Input Register along with the TC,
ACC, SUB and RND inputs.
CLKP
I Product Register Clock. The rising edge of CLKP latches the LSP, MSP and XTP Registers. If the
preload control is active, the data on the I/O ports is loaded into these registers. If preload is not ac-
tive, the accumulated product is loaded into the registers.
3-12


3Pages


HMA510883 電子部品, 半導体
AC Test Circuit
DUT
V1
R1
C1 (SEE NOTE)
HMA510/883
AC Testing Input, Output Waveforms
VIH 1.5V
VIL
1.5V
VOH
VOL
NOTE: Includes Stray and Jig Capacitance
NOTE: AC Testing: All Parameters tested as per test circuit. Input
rise and fall times are driven at 1ns/V.
Timing Diagram
DATA
INPUT
CLOCK
INPUT
tS tH
3.0V
1.5V
0V
THREE
STATE
CONTROL
3.0V
1.5V
0V
OUTPUT
THREE
STATE
1.5V
tDIS
tENA
HIGH IMPEDANCE
FIGURE 1. SET-UP AND HOLD TIME
FIGURE 2. THREE-STATE CONTROL
CLKX
CLKY
XIN, YIN
RND, TC
ACC, SUB
CLKP
tS
OUTPUT P, Y
tPWH
tPWL
tH
tHCL
tMA
tD
FIGURE 3. HMA510 TIMING DIAGRAM
tPWH
tPWL
CLKP
PREL
OEX
OEM
OEL
OUTPUT
PINS
tS tH
FIGURE 4. PRELOAD TIMING DIAGRAM
3-15

6 Page



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部品番号部品説明メーカ
HMA510883

16 x 16-Bit CMOS Parallel Multiplier Accumulator

Intersil Corporation
Intersil Corporation


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