PDF HM624100HLJP-12 Data sheet ( Hoja de datos )

Número de pieza	HM624100HLJP-12
Descripción	4M High Speed SRAM (1-Mword x 4-bit)
Fabricantes	Hitachi Semiconductor
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No Preview Available ! HM624100H Series 4M High Speed SRAM (1-Mword × 4-bit) ADE-203-789D (Z) Rev. 1.0 Sep. 15, 1998 Description The HM624100H is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The HM624100H is packaged in 400-mil 32-pin SOJ for high density surface mounting. Features • Single 5.0 V supply : 5.0 V ± 10 % • Access time 10/12/15 ns (max) • Completely static memory  No clock or timing strobe required • Equal access and cycle times • Directly TTL compatible  All inputs and outputs • Operating current : 200/180/160 mA (max) • TTL standby current : 70/60/50 mA (max) • CMOS standby ccurrent : 5 mA (max) : 1.2 mA (max) (L-version) • Data retension current : 0.8 mA (max) (L-version) • Data retension voltage : 2.0 V (min) (L-version) • Center VCC and VSS type pinout 1 page HM624100H Series DC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10 %, VSS = 0V) Parameter Symbol Min Input leakage current IILII Output leakage current IILOI Operation power supply current 10 ns cycle ICC — — — Standby power supply current 12 ns cycle ICC 15 ns cycle ICC 10 ns cycle ISB 12 ns cycle ISB 15 ns cycle ISB I SB1 — — — — — — Typ1 — — — Max 2 2 200 Unit µA µA mA — 180 — 160 — 70 mA — 60 — 50 0.1 5 mA —2 0.12 1.22 Output voltage VOL — — 0.4 V VOH 2.4 — — V Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed. 2. This characteristics is guaranteed only for L-version. Test conditions Vin = VSS to VCC Vin = VSS to VCC Min cycle CS = VIL, lout = 0 mA Other inputs = VIH/VIL Min cycle, CS = VIH, Other inputs = VIH/VIL f = 0 MHz VCC ≥ CS ≥ VCC - 0.2 V, (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC - 0.2 V IOL = 8 mA IOH = –4 mA Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Typ Input capacitance1 Cin — — Input/output capacitance1 CI/O — — Note: 1. This parameter is sampled and not 100% tested. Max 6 8 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V 5 5 Page HM624100H Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) This characteristics is guaranteed only for L-version. Parameter Symbol Min Typ*1 Max Unit Test conditions VCC for data retention VDR Data retention current I CCDR Chip deselect to data retention time t CDR 2.0 — — 50 0— — V VCC ≥ CS ≥ VCC – 0.2 V (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC – 0.2 V 800 µA VCC = 3 V, VCC ≥ CS ≥ VCC – 0.2 V (1) 0 V ≤ Vin ≤ 0.2 V or (2) VCC ≥ Vin ≥ VCC – 0.2 V — ns See retention waveform Operation recovery time tR 5 — — ms Note: 1. Typical values are at VCC = 3.0 V, Ta = +25˚C, and not guaranteed. Low VCC Data Retention Timing Waveform VCC 3.0 V VDR 2.2 V tCDR Data retention mode CS VCC ≥ CS ≥ VCC – 0.2 V 0V tR 11 11 Page

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