|
|
HM5264165A60のメーカーはHitachi Semiconductorです、この部品の機能は「64M LVTTL interface SDRAM 133 MHz/100 MHz」です。 |
部品番号 | HM5264165A60 |
| |
部品説明 | 64M LVTTL interface SDRAM 133 MHz/100 MHz | ||
メーカ | Hitachi Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとHM5264165A60ダウンロード(pdfファイル)リンクがあります。 Total 67 pages
HM5264165F-75/A60/B60
HM5264805F-75/A60/B60
HM5264405F-75/A60/B60
64M LVTTL interface SDRAM
133 MHz/100 MHz
1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank
/4-Mword × 4-bit × 4-bank
PC/133, PC/100 SDRAM
ADE-203-940B (Z)
Rev. 1.0
Nov. 10, 1999
Description
The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi
HM5264805F is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The Hitachi HM5264405F
is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs are referred to the
rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
• 3.3 V power supply
• Clock frequency: 133 MHz/100 MHz (max)
• LVTTL interface
• Single pulsed RAS
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8/full page
• 2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
1 Page HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Pin Arrangement (HM5264165F)
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
DQML
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
VCC
54-pin TSOP
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
(Top view)
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
VSS
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Pin Description
Pin name
A0 to A13
DQ0 to DQ15
CS
RAS
CAS
Function
Pin name
Function
Address input
WE Write enable
Row address A0 to A11
DQMU/DQML Input/output mask
Column address A0 to A7
CLK
Clock input
Bank select address A12/A13 (BS) CKE
Clock enable
Data-input/output
Chip select
Row address strobe command
Column address strobe command
VCC
VSS
VCCQ
VSSQ
NC
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
3
3Pages HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Block Diagram (HM5264165F)
Column address
counter
A0 to A7
Column address
buffer
A0 to A13
Row address
buffer
A0 to A13
Refresh
counter
Row decoder
Memory array
Bank 0
4096 row
X 256 column
X 16 bit
Row decoder
Memory array
Bank 1
4096 row
X 256 column
X 16 bit
Row decoder
Memory array
Bank 2
4096 row
X 256 column
X 16 bit
Row decoder
Memory array
Bank 3
4096 row
X 256 column
X 16 bit
Input
buffer
Output
buffer
DQ0 to DQ15
Control logic &
timing generator
6
6 Page | |||
ページ | 合計 : 67 ページ | ||
|
PDF ダウンロード | [ HM5264165A60 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
HM5264165A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz | Hitachi Semiconductor |