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HM5225805B-75 の電気的特性と機能

HM5225805B-75のメーカーはElpida Memoryです、この部品の機能は「256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 16-bit 4-bank/8-Mword 8-bit 4-bank /16-Mword 4-bit 4-bank PC/133/ PC/100 SDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 HM5225805B-75
部品説明 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 16-bit 4-bank/8-Mword 8-bit 4-bank /16-Mword 4-bit 4-bank PC/133/ PC/100 SDRAM
メーカ Elpida Memory
ロゴ Elpida Memory ロゴ 




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HM5225805B-75 Datasheet, HM5225805B-75 PDF,ピン配置, 機能
HM5225165B-75/A6/B6
HM5225805B-75/A6/B6
HM5225405B-75/A6/B6
256M LVTTL interface SDRAM
133 MHz/100 MHz
4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank
/16-Mword × 4-bit × 4-bank
PC/133, PC/100 SDRAM
E0082H10 (1st edition)
(Previous ADE-203-1073B (Z))
Jan. 31, 2001
Description
The HM5225165B is a 256-Mbit SDRAM organized as 4194304-word × 16-bit × 4 bank. The HM5225805B
is a 256-Mbit SDRAM organized as 8388608-word × 8-bit × 4 bank. The HM5225405B is a 256-Mbit
SDRAM organized as 16777216-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge
of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
3.3 V power supply
Clock frequency: 133 MHz/100 MHz (max)
LVTTL interface
Single pulsed RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8
2 variations of burst sequence
Sequential (BL = 1/2/4/8)
Interleave (BL = 1/2/4/8)
Programmable CAS latency: 2/3
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

1 Page





HM5225805B-75 pdf, ピン配列
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Pin Arrangement (HM5225165B)
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
DQML
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
54-pin TSOP
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
(Top view)
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
VSS
NC
DQMU
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Pin Description
Pin name
Function
A0 to A12,
BA0, BA1
Address input
Row address
A0 to A12
Column address
A0 to A8
Bank select address BA0/BA1 (BS)
DQ0 to DQ15 Data-input/output
CS Chip select
RAS
Row address strobe command
CAS
Column address strobe command
Pin name
WE
Function
Write enable
DQMU/DQML Input/output mask
CLK Clock input
CKE
Clock enable
VCC
VSS
VCCQ
VSSQ
NC
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Data Sheet E0082H10
3


3Pages


HM5225805B-75 電子部品, 半導体
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Block Diagram (HM5225165B)
Column address
counter
A0 to A8
A0 to A12, BA0, BA1
A0 to A12, BA0, BA1
Column address
buffer
Row address
buffer
Refresh
counter
Row decoder
Memory array
Bank 0
8192 row
X 512 column
X 16 bit
Row decoder
Memory array
Bank 1
8192 row
X 512 column
X 16 bit
Row decoder
Memory array
Bank 2
8192 row
X 512 column
X 16 bit
Row decoder
Memory array
Bank 3
8192 row
X 512 column
X 16 bit
Input
buffer
Output
buffer
DQ0 to DQ15
Control logic &
timing generator
Data Sheet E0082H10
6

6 Page



ページ 合計 : 30 ページ
 
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共有リンク

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部品番号部品説明メーカ
HM5225805B-75

256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 16-bit 4-bank/8-Mword 8-bit 4-bank /16-Mword 4-bit 4-bank PC/133/ PC/100 SDRAM

Elpida Memory
Elpida Memory


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