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HM-65642883 の電気的特性と機能

HM-65642883のメーカーはIntersil Corporationです、この部品の機能は「8K x 8 Asynchronous CMOS Static RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 HM-65642883
部品説明 8K x 8 Asynchronous CMOS Static RAM
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HM-65642883 Datasheet, HM-65642883 PDF,ピン配置, 機能
HM-65642/883
March 1997
8K x 8 Asynchronous
CMOS Static RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Full CMOS Design
• Six Transistor Memory Cell
• Low Standby Supply Current . . . . . . . . . . . . . . . .100µA
• Low Operating Supply Current . . . . . . . . . . . . . . . 20mA
• Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns
• Low Data Retention Supply Voltage. . . . . . . . . . . . 2.0V
• CMOS/TTL Compatible Inputs/Outputs
• JEDEC Approved Pinout
• Equal Cycle and Access Times
• No Clocks or Strobes Required
• Gated Inputs
- No Pull-Up or Pull-Down Resistors Required
• Temperature Range -55oC to +125oC
• Easy Microprocessor Interfacing
• Dual Chip Enable Control
The HM-65642/883 is a CMOS 8192 x 8-bit Static Random
Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide
standard, which allows easy memory board layouts which
accommodate a variety of industry standard ROM, PROM,
EPROM, EEPROM and RAMs. The HM-65642/883 is ideally
suited for use in microprocessor based systems. In particu-
lar, interfacing with the Intersil 80C86 and 80C88 micropro-
cessors is simplified by the convenient output enable (G)
input.
The HM-65642/883 is a full CMOS RAM which utilizes an
array of six transistor (6T) memory cells for the most stable
and lowest possible standby supply current over the full mili-
tary temperature range. In addition to this, the high stability
of the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of four
transistor or MIX-MOS (4T) devices
Ordering Information
PACKAGE
CERDIP
CLCC
TEMPERATURE RANGE
150ns/75µA
-55oC to +125oC
HM1-65642B/883
-55oC to +125oC
HM4-65642B/883
150ns/150µA
HM1-65642/883
HM4-65642/883
200ns/250µA
HM1-65642C/883
-
PKG. NO.
F28.6
J32.A
Pinouts
HM-65642/883 (CERDIP)
TOP VIEW
HM4-65642/883 (CLCC)
TOP VIEW
NC 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ0 11
DQ1 12
DQ2 13
GND 14
28 VCC
27 W
26 E2
25 A8
24 A9
23 A11
22 G
21 A10
20 E1
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A3 8
26 NC
A2 9
25 G
A1 10
24 A10
A0 11
23 E1
NC 12
22 DQ7
DQ0 13
21 DQ6
14 15 16 17 18 19 20
PIN
A
DQ
E1
E2
W
G
NC
GND
VCC
DESCRIPTION
Address Input
Data Input/Output
Chip Enable
Chip Enable
Write Enable
Output Enable
No Connections
Ground
Power
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-220
File Number 3004.1

1 Page





HM-65642883 pdf, ピン配列
HM-65642/883
TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
PARAMETER
Data Retention
Supply Current
SYMBOL
(NOTE 1)
CONDITIONS
ICCDR
HM-65642B/883
VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V
HM-65642/883
VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V
GROUP A
SUBGROUPS TEMPERATURE
1, 2, 3
-55oC TA +125oC
LIMITS
MIN MAX
- 75
UNITS
µA
1, 2, 3 -55oC TA +125oC - 150 µA
Functional Test
HM-65642C/883
VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V
FT VCC = 4.5V (Note 3)
1, 2, 3 -55oC TA +125oC - 250 µA
7, 8A, 8B -55oC TA +125oC -
-
-
NOTES:
1. All voltages referenced to device GND.
2. Typical derating 5mA/MHz increase in ICCOP.
3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH 1.5V, and VOL 1.5V.
TABLE 2. HM-65642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
LIMITS
PARAMETERS
Read/Write/
Cycle Time
Address Access
Time
Output Enable
Access Time
Chip Enable
Access Time
Write Recovery
Time
Chip Enable to
End-of-Write
Address Setup
Time
Write Enable
Pulse Width
Data Setup Time
SYMBOL
(NOTES 1, 2)
CONDITIONS
TAVAX
VCC = 4.5V and
5.5V
TAVQV VCC = 4.5V and
5.5V
TGLQV VCC = 4.5V and
5.5V
TE1LQV VCC = 4.5V and
TE2HQV 5.5V
TWHAX
TE1HAX
TE2LAX
VCC = 4.5V and
5.5V
TE1LE1H VCC = 4.5V and
TE2HE2L 5.5V
TAVWL
TAVE1L
TAVE2H
VCC = 4.5V and
5.5V
TWLWH VCC = 4.5V and
5.5V
TDVWH
TDVE1H
TDVE2L
VCC = 4.5V and
5.5V
GROUP A
SUB-
GROUPS
TEMPERATURE
9, 10, 11 -55oC TA +125oC
HM-
65642B/883
MIN MAX
150 -
9, 10, 11 -55oC TA +125oC -
150
9, 10, 11 -55oC TA +125oC -
70
9, 10, 11 -55oC TA +125oC -
150
9, 10, 11 -55oC TA +125oC 10
-
9, 10, 11 -55oC TA +125oC 90
9, 10, 11 -55oC TA +125oC 0
-
-
9, 10, 11 -55oC TA +125oC 90
9, 10, 11 -55oC TA +125oC 60
-
-
HM-
65642/883
MIN MAX
150 -
- 150
- 70
- 150
10 -
90 -
0-
90 -
60 -
HM-
65642C/883
MIN MAX UNITS
200 -
ns
- 200
-
- 70 ns
- 200 ns
10 -
ns
120 -
0-
ns
ns
120 -
80 -
ns
ns
6-222


3Pages


HM-65642883 電子部品, 半導体
HM-65642/883
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data Retention voltage and supply current are guaran-
teed over the operating temperature range. The following
rules ensure data retention:
1. The RAM must be kept disabled during data retention. This is ac-
complished by holding the E2 pin between -0.3V and GND.
2. During power-up and power-down transitions, E2 must be held
between -0.3V and 10% of VCC.
3. The RAM can begin operating one TAVAX after VCC reaches the
minimum operating voltage of 4.5V.
VCC
4.5V
VIH
E2
VCCOR
DATA RETENTION MODE
TAVAX
GND
Read Cycles
A
Q
FIGURE 1. DATA RETENTION
TAVAX
ADDRESS 1
TAVQV
ADDRESS 2
TAXQX
DATA 1
DATA 2
FIGURE 2. READ CYCLE I: W, E2 HIGH; G, E1 LOW
A
TAVQV
E1
TE1LQV
TE1LQX
E2
TE2HQV
TE2HQX
G
TGLQV
TGLQX
Q
TAVAX
TE1HQZ
TE2LQZ
TGHQZ
FIGURE 3. READ CYCLE II: W HIGH
6-225

6 Page



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部品番号部品説明メーカ
HM-65642883

8K x 8 Asynchronous CMOS Static RAM

Intersil Corporation
Intersil Corporation


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