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HS-3282 の電気的特性と機能

HS-3282のメーカーはIntersil Corporationです、この部品の機能は「CMOS ARINC Bus Interface Circuit」です。


製品の詳細 ( Datasheet PDF )

部品番号 HS-3282
部品説明 CMOS ARINC Bus Interface Circuit
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HS-3282 Datasheet, HS-3282 PDF,ピン配置, 機能
HS-3282
REFERENCE AN400
March 1997
CMOS ARINC Bus Interface Circuit
Features
• ARlNC Specification 429 Compatible
• Data Rates of 100 Kilobits or 12.5 Kilobits
• Separate Receiver and Transmitter Section
• Dual and Independent Receivers, Connecting Directly
to ARINC Bus
• Serial to Parallel Receiver Data Conversion
• Parallel to Serial Transmitter Data Conversion
• Word Lengths of 25 or 32 Bits
• Parity Status of Received Data
• Generate Parity of Transmitter Data
• Automatic Word Gap Timer
• Single 5V Supply
• Low Power Dissipation
• Full Military Temperature Range
Ordering Information
PACKAGE
CERDIP
SMD#
CLCC
SMD#
TEMP. RANGE
-55oC to +125oC
PART NUMBER
HS1-3282-8
PKG.
NO.
F40.6
-40oC to +85oC
-55oC to +125oC
5962-8688001QA
HS4-3282-9+
HS4-3282-8
F40.6
J44.A
J44.A
5962-8688001XA J44.A
Description
The HS-3282 is a high performance CMOS bus interface
circuit that is intended to meet the requirements of ARINC
Specification 429, and similar encoded, time multiplexed
serial data protocols. This device is intended to be used with
the HS-3182, a monolithic Dl bipolar differential line driver
designed to meet the specifications of ARINC 429. The
ARINC 429 bus interface circuit consists of two (2) receivers
and a transmitter operating independently as shown in
Figure 1. The two receivers operate at a frequency that is ten
(10) times the receiver data rate, which can be the same or
different from the transmitter data rate. Although the two
receivers operate at the same frequency, they are
functionally independent and each receives serial data asyn-
chronously. The transmitter section of the ARINC bus
interface circuit consists mainly of a First-In First-Out (FIFO)
memory and timing circuit. The FIFO memory is used to hold
up to eight (8) ARINC data words for transmission serially.
The timing circuit is used to correctly separate each ARINC
word as required by ARINC Specification 429. Even though
ARINC Specification 429 specifies a 32-bit word, including
parity, the HS-3282 can be programmed to also operate with
a word length of 25 bits. The incoming receiver data word
parity is checked, and a parity status is stored in the receiver
latch and output on Pin BD08 during the 1st word. [A logic
“0” indicates that an odd number of logic “1” s were received
and stored; a logic “1” indicates that an even number of logic
“1”s were received and stored]. In the transmitter the parity
generator will generate either odd or even parity depending
upon the status of PARCK control signal. A logic “0” on BD12
will cause odd parity to be used in the output data stream.
Versatility is provided in both the transmitter and receiver by
the external clock input which allows the bus interface circuit
to operate at data rates from 0 to 100 kilobits. The external
clock must be ten (10) times the data rate to insure no data
ambiguity.
The ARINC bus interface circuit is fully guaranteed to
support the data rates of ARINC specification 429 over both
the voltage (±5%) and full military temperature range. It
interfaces with UL, CMOS or NMOS support circuitry, and
uses the standard 5-volt VCC supply.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-183
File Number 2964.2

1 Page





HS-3282 pdf, ピン配列
HS-3282
Pin Description
PIN SYMBOL SECTION
DESCRIPTION
1 VCC Recs/Trans Supply pin 5 volts ±5%.
2
429 DI1 (A)
Receiver ARlNC 429 data input to Receiver 1.
3
429 DI1 (B)
Receiver ARlNC 429 data input to Receiver 1.
4
429 Dl2 (A)
Receiver ARINC 429 data input to Receiver 2.
5
429 DI2 (B)
Receiver ARINC 429 data input to Receiver 2.
6
D/R1
Receiver Device ready flag output from Receiver 1 indicating a valid data word is ready to be fetched.
7
D/R2
Receiver Device ready flag output from Receiver 2 indicating a valid data word is ready to be fetched.
8 SEL Receiver Bus Data Selector - Input signal to select one of two 16-bit words from either Receiver 1 or 2.
9 EN1 Receiver Input signal to enable data from Receiver 1 onto the data bus.
10 EN2 Receiver Input signal to enable data from Receiver 2 onto the data bus.
11
BD15
Recs/Trans Bi-directional data bus for fetching data from either of the Receivers, or for loading data into
the Transmitter memory or control word register. See Control Word Table for description of
Control Word bits.
12
BD14
Recs/Trans See Pin 11.
13
BD13
Recs/Trans See Pin 11.
14
BD12
Recs/Trans See Pin 11.
15
BD11
Recs/Trans See Pin 11.
16
BD10
Recs/Trans See Pin 11.
17
BD09
Recs/Trans See Pin 11.
18
BD08
Recs/Trans See Pin 11.
19
BD07
Recs/Trans See Pin 11.
20
BD06
Recs/Trans See Pin 11.
21
GND
Recs/Trans Circuit Ground.
22
BD05
Recs/Trans See Pin 11.
23
BD04
Recs/Trans See Pin 11. Control Word function not applicable.
24
BD03
Recs/Trans See Pin 11. Control Word function not applicable.
25
BD02
Recs/Trans See Pin 11. Control Word function not applicable.
26
BD01
Recs/Trans See Pin 11. Control Word function not applicable.
27
BD00
Recs/Trans See Pin 11. Control Word function not applicable.
28 PL1 Transmitter Parallel load input signal loading the first 16-bit word into the Transmitter memory.
29 PL2 Transmitter Parallel load input signal loading the first 16-bit word into the Transmitter memory and initiates
data transfer into the memory stack.
30
TX/R
Transmitter Transmitter flag output to indicate the memory is empty.
5-185


3Pages


HS-3282 電子部品, 半導体
HS-3282
TABLE 2B. WORD 2 FORMAT
BI-DIRECTIONAL
BlT#
15
14
13 - 00
FUNCTION
Sign
MSB
Data
ARINC BIT#
29
28
27 - 14
Receiver Parity Status:
0 = Odd Parity
1 = Even Parity
If the receiver input data word string is broken before the
entire data word is received, the receiver will reset and
ignore the partially received data word.
If the transmitter is used to transmit consecutive data words,
each word will be separated by a four (4) bit “null” state (both
positive and negative outputs will maintain a zero (0) volt
level.)
TABLE 3. ARINC 25-BIT DATA FORMAT
ARINC BIT #
1-8
9
11 - 23
24
25
FUNCTION
Label
LSB
Data
MSB
Parity Status
TABLE 4A. WORD 1 FORMAT
BI-DIRECTIONAL
BIT#
15 - 9
8
7-0
FUNCTION
Don’t Care
Parity Status
Label
ARINC BIT#
XXX
25
1-8
TABLE 4B. WORD 2 FORMAT
BI-DIRECTIONAL
BIT#
15
14 - 1
0
FUNCTION
MSB
Data
LSB
ARINC BlT#
24
23 -10
9
Receiver Parity Status:
0 = Odd Parity
1 = Even Parity
No Source/Destination (S/D) in 25-Bit format.
Receiver Operation
Since the two receivers are functionally identical, only one
will be discussed in detail, and the block diagram will be
used for reference in this discussion. The receiver consists
of the following circuits:
• The Line Receiver functions as a voltage level translator.
It transforms the 10 volt differential line voltage, ARINC
429 format, into 5 volt internal logic level.
• The output of the Line Receiver is one of two inputs to the
Self-Test Data Selector (SEL). The other input to the
Data Selector is the Self-Test Signal from the Transmitter
section.
• The incoming data, either Self-Test or ARlNC 429, is
double sampled by the Word Gap Timer to generate a
Data Clock. The Receiver sample frequency (RCVCLK),
1MHz, or 125kHz, is generated by the Receiver/Transmit-
ter Timing Circuit. This sampling frequency is ten times the
Data Rate to ensure no data ambiguity.
• The derived data clock then shifts the data down a 32-Bit
long Data Shift Register (Data S/RI). The Data Word
Length is selectable for either 25 Bits or 32 Bits long by the
Control Signal (WLSEL). As soon as the data word is
completely received, an internal signal (WDCNT1) is gen-
erated by the Word Gap Timer Circuit.
• The Source/Destination (S/D) Decoder compares the user
set code (X and Y) with Bits 9 and 10 of the Data Word. If
the two codes are matched, a positive signal is generated
to enable the WDCNT1 signal to latch in the received data.
Otherwise, the data word is ignored and no latching action
takes place. The S/D Decoder can be Enabled and
Disabled by the control signal S/D ENB. If the data word is
latched, an indicator flag (D/R1) is set. This indicates a
valid data word is ready to be fetched by the user.
• After the receiver data has been shifted down the shift
register, it is placed in a holding register. The device ready
flag will then be set indicating that data is ready to be
fetched. If the data is ignored and left in the holding regis-
ter, it will be written over when the next data word is
received.
• The received data in the 32-bit holding register is placed
on the bus in the form of two (2)16-bit words regardless of
whether the format is for 32 or 25-bit data words. Either
word can be accessed first or repeatedly until the next
received data word falls into the holding register.
• The parity of the incoming word is checked and the status
(i.e., logic “0” for odd parity and logic “1” for even parity)
stored in the receiver latch and output on BD08 during the
Word No. 1.
• Assuming the user desires to access the data, he first sets
the Data Select Line (SEL) to a Logic “0” level and pulses
the Enable (EN1) line. This action causes the Data
Selector (SELl) to select the first-data word, which con-
tains the label field and Enable it onto the Data Bus. To
obtain the second data word, the user sets the SEL line to
a Logic “1” level and pulse the Enable (EN1) line again.
The Enable pulse duration is matched to the user circuit
requirement needed to read the Data Word from the Data
Bus. The second Enable pulse is also used to reset the
Device Ready (D/R1) flip-flop. This completes a receiving
cycle.
5-188

6 Page



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部品番号部品説明メーカ
HS-3282

CMOS ARINC Bus Interface Circuit

Intersil Corporation
Intersil Corporation


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