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HS-139RH の電気的特性と機能

HS-139RHのメーカーはIntersil Corporationです、この部品の機能は「Radiation Hardened Quad Voltage Comparator」です。


製品の詳細 ( Datasheet PDF )

部品番号 HS-139RH
部品説明 Radiation Hardened Quad Voltage Comparator
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HS-139RH Datasheet, HS-139RH PDF,ピン配置, 機能
DATASHEET
Radiation Hardened Quad Voltage Comparator
HS-139RH, HS-139EH
The Radiation Hardened HS-139RH, HS-139EH consists of four
independent single or dual supply voltage comparators on a
single monolithic substrate. The common mode input voltage
range includes ground, even when operated from a single
supply and the low supply current makes these comparators
suitable for low power applications. These types were designed
to directly interface with TTL and CMOS.
The HS-139RH, HS-139EH are fabricated on our dielectrically
isolated Rad Hard Silicon Gate (RSG) process, which provides
an immunity to Single Event Latch-up and the capability of
highly reliable performance in any radiation environment.
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HS-139RH, HS-139EH
are contained in SMD 5962-98613. A “hot-link” is provided on
our homepage with instructions for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Features
• QML qualified per MIL-PRF-38535 requirements
• Radiation environment
- Latch-up free under any conditions
- Total dose (Max) . . . . . . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si)
- SEU LET threshold . . . . . . . . . . . . . . . . . . . 20MeV/cm2/mg
- Low dose rate effects immunity
• 100V output voltage withstand capability
• ESD protection to >3000V
• Differential input voltage range equal to the supply voltage
• Input offset voltage (VIO). . . . . . . . . . . . . . . . . . . . . 2mV (Max)
• Quiescent supply current . . . . . . . . . . . . . . . . . . . . 2mA (Max)
• Pb-Free (RoHS Compliant)
Applications
• Pulse generators
• Timing circuitry
• Level shifting
• Analog-to-digital conversion
Pin Configurations
HS-139RH, HS-139EH
(SBDIP CDIP2-T14)
TOP VIEW
OUT 2 1
OUT 1 2
V+ 3
- IN 1 4
+ IN 1 5
- IN 2 6
+ IN 2 7
14 OUT 3
13 OUT 4
12 GND
11 + IN 4
10 - IN 4
9 + IN 3
8 - IN 3
OUT 2
OUT 1
V+
- IN 1
+ IN 1
- IN 2
+IN 2
HS-139RH, HS-139EH
(FLATPACK CDFP3-F14)
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
OUT 3
OUT 4
GND
+ IN 4
- IN 4
+ IN 3
- IN 3
August 8, 2013
FN3573.6
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 1999, 2004, 2008, 2009, 2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 Page





HS-139RH pdf, ピン配列
HS-139RH, HS-139EH
Die Characteristics
DIE DIMENSIONS:
3750µm x 2820µm (148 mils x 111 mils)
483µm ±25.4µm (19 mils ±1 mil)
INTERFACE MATERIALS:
Glassivation:
Type: Silox (SiO2)
Thickness: 8.0kÅ ±1.0kÅ
Top Metallization:
Type: AlSiCu
Thickness: 16.0kÅ ±2kÅ
Metallization Mask Layout
Substrate:
Radiation Hardened Silicon Gate, Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 105 A/cm2
Transistor Count:
49
HS-139RH, HS-139EH
GND +IN4
(12) (11)
-IN4
(10)
OUT4
(13)
OUT3
(14)
OUT2
(1)
OUT1
(2)
V+ -IN1
(3) (4)
+IN1
(5)
+IN3
(9)
-IN3
(8)
+IN2
(7)
-IN2
(6)
3 FN3573.6
August 8, 2013


3Pages


HS-139RH 電子部品, 半導体
HS-139RH, HS-139EH
Ceramic Metal Seal Flatpack Packages (Flatpack)
e
-A-
PIN NO. 1
ID AREA
A
A
-B- D
S1
b
E1
0.004 M H A - B S D S
0.036 M H A - B S D S
Q
A
-C-
SEATING AND
BASE PLANE
E -D-
L E2
E3 E3
c1 LEAD FINISH
L
C
-H-
BASE
METAL
(c)
b1
NOTES:
MM
(b)
SECTION A-A
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark. Alternately, a tab (dimension k) may be
used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits
of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass over-
run.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness. The maximum limits of
lead dimensions b and c or M shall be measured at the centroid of
the finished lead surfaces, when solder dip or tin plate lead finish is
applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materi-
als shall be molded to the bottom of the package to cover the leads.
8. Dimension Q shall be measured at the point of exit (beyond the me-
niscus) of the lead from the body. Dimension Q minimum shall be
reduced by 0.0015 inch (0.038mm) maximum when solder dip lead
finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D - 0.390 - 9.91 3
E
0.235
0.260
5.97
6.60
-
E1 - 0.290 - 7.11 3
E2 0.125 - 3.18
-
-
E3 0.030 - 0.76 - 7
e 0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
2
L
0.270
0.370
6.86
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1 0.005 - 0.13 - 6
M
-
0.0015
-
0.04
-
N 14
14 -
Rev. 0 5/18/94
6 FN3573.6
August 8, 2013

6 Page



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共有リンク

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部品番号部品説明メーカ
HS-139RH

Radiation Hardened Quad Voltage Comparator

Intersil Corporation
Intersil Corporation
HS-139RH-T

Radiation Hardened Quad Voltage Comparator

Intersil Corporation
Intersil Corporation


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