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PDF HRF3205 Data sheet ( Hoja de datos )
| Número de pieza | HRF3205 | |
| Descripción | 100A/ 55V/ 0.008 Ohm/ N-Channel/ Power MOSFETs | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
HRF3205, HRF3205S
June 1999 File Number 4447.4
100A, 55V, 0.008 Ohm, N-Channel, Power
MOSFETs
These are N-Channel enhancement mode silicon gate
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specified level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
converters, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. These types can be operated directly
from integrated circuits.
NOTE: Calculated continuous current based on maximum
allowable junction temperature. Package limited to 75A
continuous, see Figure 9.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HRF3205
TO-220AB
HRF3205
HRF3205S
TO-263AB
HRF3205S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the TO-263AB variant in tape and reel, e.g., HRF3205ST.
Packaging
DRAIN
(FLANGE)
JEDEC TO-220AB
SOURCE
DRAIN
GATE
Features
• 100A, 55V (See Note)
• Low On-Resistance, rDS(ON) = 0.008Ω
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
4-29
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
HRF3205, HRF3205S
Typical Performance Curves (Continued)
10
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
1 0.01
0.1
0.01
10-5
PDM
SINGLE PULSE
10-4
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
100
101
FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01Ω
0
tP
IAS
BVDSS
VDS
VDD
tAV
FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT
VDS
RL
VGS
IG(REF)
DUT
+
VDD
-
FIGURE 14. GATE CHARGE TEST CIRCUIT
FIGURE 13. UNCLAMPED ENERGY WAVEFORMS
VDD
Qgs
0
Qg(TOT)
Qgd
VGS
VDS
IG(REF)
0
FIGURE 15. GATE CHARGE WAVEFORM
4-33
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HRF3205.PDF ] | |
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