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HV9904 の電気的特性と機能

HV9904のメーカーはSupertex Incです、この部品の機能は「HV9904 Multi Converter Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 HV9904
部品説明 HV9904 Multi Converter Controller
メーカ Supertex Inc
ロゴ Supertex  Inc ロゴ 




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HV9904 Datasheet, HV9904 PDF,ピン配置, 機能
HV9904
Preliminary Engineering Specification
HV9904 Multi Converter Controller
Features
General Description
‰ Eliminates High Voltage Input Electrolytic Capacitor
‰ Smallest and Most Reliable Off-Line Solution
‰ Constant Current or Constant Voltage Mode Control
‰ Can be Operated Directly from Rectified AC Mains
‰ 10V to 400V Input Range Internal Regulator
‰ 1.5mA Operating Supply Current
‰ PLL Based Loop Control with Soft Start
‰ On-Time Varies Inversely with Input Voltage
‰ Frequency Varies with Load
‰ 2.5V Differential Sense
‰ Recommended for <10W Applications
Applications
‰ Universal Input Voltage LED driver
‰ Constant Current Source
‰ Battery Charger
Ordering Information
Package Options
8 Pin Plastic DIP
8 Pin SOIC
HV9904P
HV9904LG
Dice
HV9904X
The Supertex HV9904 is a second order PWM controller designed
to provide a constant average current output or a constant average
voltage output from an input of 10V to 400V DC or directly from
rectified AC mains up to 280V. The second order topology is
capable of extremely high dynamic control range, allowing
operation directly from rectified AC mains without the need for
bulky and expensive high voltage input electrolytic capacitor.
The PWM control utilizes feed forward circuitry to compensate for
large variations in input voltage (i.e. rectified AC) and a novel
integrator lock loop PLL scheme to regulate a differentially sensed
feedback node where the signal may be discontinuous. This
feedback node could be a current sense resistor or divider from
regulated output voltage. For a constant load the switching
frequency will be nearly constant with a dither of a few kHz helping
to meet FCC conducted emissions requirements.
A high input voltage linear regulator provides a stable Vdd supply
for the internal circuitry and gate drive to the external MOSFET.
Under voltage lockout provides a power on reset and protection for
the MOSFET
Typical Application Circuit
Universal Input Constant Average Currrent LED Lamp Power Supply
10VDC to 400VDC
or
VAC to 265V
1N4007
D1 D2
D5 D6
MURS120T3 MURS120T3
L2
220uH
D4 D3
C3
0.01uF
D7
MURS120T3
C1
0.1uF
400V
L1
1mH
U1
Vdd +Vin GATE M1
NS
HV9904
C2 PS
1uF AGND PGND
VN2460N8
or
IRFBC30AS
C4
0.1uF
10mA
1 to 8
LEDs
R1
250
Prepare by Telecom Group
1
Rev. D
3/29/2002
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

1 Page





HV9904 pdf, ピン配列
HV9904
Pinout
Pin Description
+Vin 1
NC 2
Vdd 3
HV9904
8 GATE
7 PGND
6 NS
+VIN This is the input to the internal linear regulator that provides
the constant voltage VDD internal supply for the PWM. It can
accept DC input voltages in the range of 10 to 400 Volts.
VDD This is the output of the internal linear regulator and the
supply pin for the PWM circuits. It must be bypassed with a
capacitor capable of storing sufficient energy so that the voltage
does not decay below the UVLO threshold during the time when
the input voltage is below the minimum required by the regulator.
NC – No internal connection to this pin.
AGRD – Common connection for analog circuits.
AGND 4
5 PS
GATE – This is the PWM output for driving the gate of an N-
channel external MOSFET.
PGRD – Common connection for GATE drive circuit.
NS – This is negative sense input to the PWM control circuit.
PS – This is positive sense input to the PWM control circuit
__________________________________________________________________________________________________________________
Functional Block Diagram
+Vin
Vdd
AGND
Regulator
Vdd
Reference
UVLO
Vref
Variable Frequency and
Duty Cycle Oscillator
Gate
Driver
Integrator
Differential
Sense
GATE
PGND
PS
NS
Functional Description
On initial power application the high input voltage (10V to 400V)
linear regulator charges the capacitor connected to Vdd and seeks
to provide a stable supply for the internal circuitry and gate drive to
the external MOSFET. Under voltage lockout (UVLO) holds the
oscillator disabled and reset to its lowest frequency state until the
Vdd supply rises above 8Volts assuring sufficient gate drive
voltage for the external MOSFET. Once Vdd is above the UVLO
threshold the oscillator is enabled and the external MOSFET is
driven via the gate driver at the oscillator frequency. The UVLO
has a 0.5V hysteresis to prevent false triggering due to ripple on
Vdd.
The duty cycle of the oscillator output and thus the on time of the
MOSFET is determined by a feed forward circuit that sets the
maximum on time based on the instantaneous value of the input
voltage, thus avoiding core saturation of the magnetic elements.
The oscillator is initially operating at its lowest frequency and
continues to operate at this low frequency for several cycles to
assure that a stable equilibrium state is reached. After this initial
delay the feedback circuit is enabled and the oscillator frequency is
increased in small steps on oscillator cycles until the PWM output
(current or voltage) reaches the programmed value. Since the rate
of increase in frequency is a function of the frequency the oscillator
frequency will rise exponentially.
The differential sense circuit monitors the programming node
(voltage on current sense resistor for constant average current
control or voltage on resistive divider for constant average voltage
control) using an integrator lock loop feedback to obtain a stable
average value from even a discontinuous signal. As long as this
average value is less than 2.5V the oscillator frequency is
incremented. When the average value reaches 2.5V the oscillator
frequency incrementing is halted. If the average value exceeds
2.5V then the oscillator frequency is decremented. In this manner
the oscillator frequency is dithered to maintain output regulation
while the feed forward sensing of the input voltage maintains a
fixed value of energy transfer per oscillator cycle.
Line regulation is controlled by the instantaneous feed forward
sensing of the input voltage, thus the PWM can easily track a full
wave rectified sine wave of input voltage at 50Hz, 60Hz or 400Hz
provided that the capacitor connected at Vdd can store sufficient
energy to prevent decay below the UVLO threshold during the time
when the resulting input voltage at +Vin is below 10V. For a 50Hz
rectified sine wave a 1µF capacitor connected to Vdd is sufficient
to guarantee stable operation at 50Hz.
Load regulation is controlled via the feedback sensing circuit by
adjusting the oscillator frequency to maintain average energy
transfer consistent with the load conditions. For relatively stable
load conditions this method achieves excellent regulation. For a
constant load the switching frequency will be nearly constant with a
dither of a few kHz helping to meet FCC conducted emissions
requirements.
Prepare by Telecom Group
3
Rev. D
3/29/2002
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com


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