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HV9606 の電気的特性と機能

HV9606のメーカーはSupertex Incです、この部品の機能は「HV9606 Current-Mode PWM Controller with Supervisor」です。


製品の詳細 ( Datasheet PDF )

部品番号 HV9606
部品説明 HV9606 Current-Mode PWM Controller with Supervisor
メーカ Supertex Inc
ロゴ Supertex  Inc ロゴ 




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HV9606 Datasheet, HV9606 PDF,ピン配置, 機能
HV9606
Initial Release
HV9606 Current-Mode PWM Controller with Supervisor
Features
Synchronous Forward, Forward, and Flyback Controller
Lowest External Parts Count, Smallest Magnetics
Eliminates Bootstrap Transformer Winding
Supervisor Circuit Reduces Output Capacitance* up to 40%
Supervisor Circuit Functions as µP Supply Monitor and POR
15V to 250V Start-Up Regulator with START/STOP Control
<1mA Operating, <6µA Standby Input Current
VDD Powered Operation down to 2.9V
Charge Pump Gate Drive Supply
Programmable Soft Start
Under Voltage Lockout with Programmable Hysteresis
<50% Duty Cycle Operation
15kHz to 400kHz Fixed Frequency PWM Operation
Fault Tolerant Peer-to-Peer Synchronization
Precision !1% Band Gap Voltage Reference
Current Sense Leading Edge Blanking
Small SSOP-20 Footprint
*For short duration line loss, supervisor disables soft start if output
within tolerance when VIN returns and thus reduces holdup
requirements.
Applications
Powered Ethernet and VoIP Terminals
Cable Modems and Amplifiers
ISDN Network Terminations, Terminals and Adapters
Network Equipment
Servers, PCs and Peripheral Equipment
Telecommunication Systems and Terminals
Distributed Board Mounted Power
Battery Backup Systems
Portable Power Applications
Automotive and Heavy Equipment
General Description
The HV9606 PWM controller allows the design of high efficiency
(>90%) power supplies for distributed board mounted power (BMP)
applications. Due to its high frequency capability it can provide
high currents (20A @ 3.3V) with small transformers and due to its
low internal operating voltage and current is also able to achieve
high efficiencies in low power applications.
The HV9606 utilizes fixed frequency current mode control with duty
cycle internally limited to <50%. It supports both isolated and non-
isolated topologies and provides all the necessary functions to
implement a flyback, forward or synchronous forward converter
with a minimum of external parts. Due to its low VDD operation the
bootstrap magnetic winding is eliminated in non-isolated
topologies. An on chip charge pump generates the gate drive
voltage for driving an external N-channel MOSFET and eliminates
the need for clamping by offering 250V immunity to high voltage
transients common in telecom and network systems. It conforms
to the requirements of IEEE 802.3 Powered Ethernet and ETR-080
ISDN specifications.
The oscillator is programmable and provides fault tolerant peer-to-
peer synchronization to other similar circuits or master clock. The
chip draws almost no current (<6µA @ VIN < 20V) until the
programmable START/STOP thresholds of the start-up regulator
are satisfied. It can also be powered via the VDD pin, rather than
the VIN pin, in the range of 2.9V to 5.5V.
Other functions include leading edge current sense blanking,
programmable SOFT START, precision !1% band gap reference
and a SUPERVISOR CIRCUIT. The SUPERVISOR can provide
housekeeping functions such as µP supply monitoring and reset,
soft start inhibit for rapid restart on short duration input voltage
interruption. It also minimizes input and output capacitance
requirements.
Typical Application Circuit
+48V
GND
R3
R2
R1
C1
10W Non-Isolated 48V to 3.3V Flyback Converter
C2
C4
C3
R4
1 VDD
2 START
3 STOP
4 Vin
5 REF
6 SS
7 SYNC
8 RT
9 SGND
10 PGND
STATUS 20
SENSE 19
FB
COMP
18
C7
17
NI 16
CA 15
CB 14
VX2 13
GATE 12
CS 11
C9
C8
R6
C6
C5
T1
M1
R5
D1
R7
R8
R9
To SYNC pin of other HV9606 PWMs.
To uP
RESET
Q1 Pin.
+3.3V
C10
R10
GND
1 4/15/2002-R.L2
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

1 Page





HV9606 pdf, ピン配列
Electrical Characteristics – Continued
Symbol
Parameter
Min Typ Max Units
HV9606
Test Conditions
Reference
VREF
Reference output voltage
VREF Reference output voltage tolerance
VREF Reference output voltage tolerance
VREF
Load regulation
VREF
Line regulation
IREF(SHORT)
Short circuit current
1.2402
2
2
1
2
5
5
3
V TA = 25ºC, 2.4V VDD 5.5V
% TA = 25ºC, 2.4V VDD 5.5V
% -40ºC TA 85ºC, 2.4V VDD 5.5V
mV 0 < IREF < 0.1 mA
mV 2.4V VDD 5.5V
mA VREF = GND
Current Sensing (Test conditions: VDD = 3.3V)
VCS Usable control current sense range
VCS Current limit threshold
VCS Leading edge current sense blanking time
tDELAY
Current limit delay to output
0 0.59
0.48VREF 0.50VREF 0.52VREF
85
70 120
V
V
nSec
nSec
VCS = 0 to 1V step after blanking time
Error Amplifier (Test conditions: 2.9V VDD 5.5V)
IFB or INI
Input bias current
VFB - VNI
Input offset voltage
VCM
AVOL
Common mode input range
Open loop voltage gain
BW Unity gain bandwidth
ISOURCE
Output current sourcing
ISINK Output current sinking
VCOMP
PSRR
Output voltage range
Power supply rejection
0
65
1
1
-100
0
50
25 200 nA VFB = 1.5V, VNI = 1.5V
±3 mV VFB = VCOMP, VNI = 1.5V
VDD–0.1
V
dB
MHz
2 mA VFB < VNI
µA VFB > VNI
VDD–0.7
V
dB FOSC = 100 kHz
Soft Start
VSS(LOW)
Soft start low output
VSS(HI)
Soft start high output
ISS(HI)
Soft start output current
tF Soft start output fall time
0.1 V VDD = 2.9V, VSENSE = 0V, VCS = 2.9V
2.5 VDD V VDD = 2.9V, VSENSE = 2.9V, VCS = 2.9V
10 20 µA VDD = 2.9V, VSENSE = 2.9V, VCS = 2.9V
10 µSec CSS = 0.1µF
Status Output (Test conditions: 2.7V VDD 5.5V)
ISINK Output current sinking
5
10
mA VSTATUS = 0.5V
ISOURCE
Output current sourcing
10 20 µA VSTATUS = (VDD - 0.5V)
VSTATUS(HIGH) High output voltage
VDD-0.1
VDD V No load
VSTATUS(LOW)
VSENSE(THLH)
Low output voltage
Sense input threshold for rising input
VSENSE(THHL) Sense input threshold for falling input
0.1 0.2
V Sinking 2mA
0.85VREF 0.85VREF 0.85VREF
+ 0.050 + 0.075 + 0.100
V
VSTATUS = LOW to HIGH transition
0.85VREF 0.85VREF 0.85VREF
- 0.050 - 0.075 - 0.100
V
VSTATUS = HIGH to LOW transition
VSENSE(HYST) Sense input hysteresis
100 150 200 mV
3 4/15/2002-R.L2
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com


3Pages


HV9606 電子部品, 半導体
Functional Description – Continued
Start-Up Regulator
The start-up regulator guarantees a maximum VIN pin leakage
current of 6µA at 20V at the VIN pin while it is inhibited by the
START/STOP circuit. When the effective input voltage exceeds
the programmed START voltage, the regulator is turned on and
seeks to provide a nominal 2.9V at the VDD pin, which is the supply
voltage for all internal circuitry within the HV9606 except the
start/stop circuit. This regulator is capable of input voltages up to
250 Volts, which is the typical maximum arrester voltage limit used
to provide protection on telephone wires. Due to the high voltage
rating of the regulator the HV9606 can be used for applications
operating from rectified AC mains up to 140Vrms. The regulator
can supply a minimum of 5mA, which is sufficient to power the
internal circuitry and provide gate drive power for the external
MOSFET until the bootstrap circuit from the output of the PWM
drives the voltage on the VDD pin higher than the regulator set
point. This forces the regulator to turn off and reduce the input
current at the Vin pin to leakage levels. The VDD pin is typically
bypassed with a capacitor of at least 1µF, which provides the peak
currents required by the voltage doubler and in turn the gate driver
for the external MOSFET.
For low power applications the circuit may be operated without
bootstrapping. Care should be taken to assure that the power
dissipation in the regulator does not become excessive, as it might
be if the input voltage is high and the gate drive energy required is
high (operating at high frequency).
Low voltage operation of the HV9606 is also possible by powering
VDD from supply voltages of 2.9V to 5.5V. In these applications the
Vin, START and STOP pins should be connected to SGND pin.
When powering only via VDD, the START/STOP control is not
available and the startup regulator circuit is not used.
VDD Under Voltage Lockout
To guarantee correct operation, internal circuitry is held reset by an
under voltage lockout (VDD UVLO) until the regulator output voltage
is at least 100mV below the startup regulator set point. To
guarantee stable starting the VDD UVLO has a hysteresis of
100mV.
Oscillator
The oscillator circuit operates at twice the PWM output frequency.
The frequency can be programmed in the range of 30kHz to
800kHz by means of a single resistor connected from the RT pin to
SGND. For a given frequency the value of the resistor can be
calculated using the following equation:
RT = [(1 / fOSC) –1x10-7] / 42.6x10-12
HV9606
Synchronization
The SYNC pin is an input/output (I/O) port to a unique fault tolerant
peer-to-peer and/or to master clock synchronization circuit. For
synchronization the SYNC pins of multiple HV9606 based
converters can be connected together and may also be connected
to the open drain/collector output of an external master clock.
When connected in this manner the oscillators will lock to the
device with the highest operating frequency. The LOW duty cycle
of an external master clock should not exceed 50%. When
synchronized in this manner, a permanent logic HIGH or LOW
condition on the SYNC pin will result in a loss of synchronization,
but the HV9606 based converters will continue to operate at their
individually set operating frequency. For this reason the SYNC pin
is considered fault tolerant, since loss of synchronization will not
result in total system failure.
Depending on the cumulative parasitic capacitance on the SYNC
pin when connected in the above manner a pull up resistor may be
required from the SYNC pin to the VDD pin on each HV9606 based
DC/DC converter circuit. The value of the resistor will depend on
the cumulative parasitic capacitance and operating frequency.
Voltage Doubler
The HV9606 can operate on internal voltages ranging from 2.9V to
5.5V. It may be difficult to find power MOSFETs capable of
operating with such low gate drive voltages. For this reason the
HV9606 incorporates a voltage doubler circuit that generates a
voltage on the VX2 pin that is approximately two times the VDD
voltage. This circuit uses capacitive charge transfer methods and
requires the connection of a capacitor (typically 0.01µF) between
the CA and CB pins as well as an energy storage capacitor
(typically 0.1µF) connected from the VX2 pin to PGND pin. The
voltage doubler operates at the PWM output frequency.
The gate driver output on the GATE pin operates from the VX2
voltage, logic level (5Volt) gate power MOSFETs may be used
when VDD is bootstrapped at 3.3V or standard (10V) gate
MOSFETs may be used when VDD is bootstrapped at 5V.
VX2 Under Voltage Lockout
To guarantee that sufficient gate drive voltage is available, an
under voltage lockout circuit (VX2 UVLO) monitors the VX2
voltage. If the VX2 voltage drops below 4.5V the gate driver output
of the PWM circuit is inhibited to prevent damage to the power
MOSFET. This under voltage lockout has a hysteresis of 400mV
to prevent spurious operation.
Band Gap Reference
The operating limits of all internal circuits, except the
START/STOP circuit, are based on the !1% tolerance band gap
reference voltage available on the REF pin. It is capable of
delivering 100µA for use by external circuitry without degrading the
reference. A bypass capacitor of at least 0.1µF should be
connected from the REF pin to SGND pin.
6 4/15/2002-R.L2
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

6 Page



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