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HV507PG の電気的特性と機能

HV507PGのメーカーはSupertex Incです、この部品の機能は「64-Channel Serial to Parallel Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 HV507PG
部品説明 64-Channel Serial to Parallel Converter
メーカ Supertex Inc
ロゴ Supertex  Inc ロゴ 




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HV507PG Datasheet, HV507PG PDF,ピン配置, 機能
Supertex inc.
HV507
64-Channel Serial to Parallel Converter
With High Voltage Push-Pull Outputs
Features
Processed with HVCMOS® technology
Operating output voltages to 300V
Low power level shifting from 5.0 to 300V
Shift register speed: 8.0MHz @ VDD = 5.0V
64 latched data outputs
Output polarity and blanking
CMOS compatible inputs
Forward and reverse shifting options
General Description
The HV507 is a low voltage serial to high voltage parallel
converter with 64 push-pull outputs. This device has been
designed for use as a printer driver for electrostatic applications.
It can also be used in any application requiring multiple output,
high voltage, low current sourcing and sinking capabilities.
The device consists of a 64-bit shift register, 64 latches, and
control logic to perform the polarity select and blanking of the
outputs. A DIR pin controls the direction of data shift through
the device. With DIR grounded, DIOA is Data-In and DIOB is
Data-Out; data is shifted from HVOUT64 to HVOUT1. When DIR
is at logic high, DIOB is Data-In and DIOA is Data-Out: data is
then shifted from HVOUT1 to HVOUT64. Data is shifted through
the shift register on the low to high transition of the clock. Data
output buffers are provided for cascading devices. Operation
of the shift register is not affected by the LE (latch enable), BL
(blanking), or the POL(polarity) inputs. Transfer of data from the
shift register to the latch occurs when the LE is high. The data in
the latch is stored during LE transition from high to low.
Functional Block Diagram
POL
BL
Latch Enable
DIOA
CLOCK
64 bit
Static Shift
DIR Register
64
Latches
DIOB
VPP
L/T
L/T
L/T
L/T
L/T = Level Translator
HVOUT1
HVOUT2
60 Additional
Outputs
HVOUT63
HVOUT64
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com

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HV507PG pdf, ピン配列
HV507
Electrical Characteristics
DC Characteristics (For VDD = 5.0V, VPP = 300V, TA = 25°C)
Sym Parameter
Min
Max Units Conditions
IDD VDD supply current
IDDQ Quiescent VDD supply current
IPP High voltage supply current
IIH High-level logic input current
IIL Low-level logic input current
VOH High level output
HVOUT
Data Out
VOL Low level output
HVOUT
Data Out
VOC HVOUT clamp voltage
- 15 mA fCLK = 8.0MHz, FDATA = 4.0MHz, LE = low
- 200 µA All VIN = 0 or VDD
-
0.50
mA VPP = 300V. All outputs high.
- 0.50
VPP = 300V. All outputs low.
- 10 µA VIH = VDD
- -10 µA VIL = 0V
265
VDD -1.0V
-
-
V
VPP = 300V, IHVOUT = -1.0mA,
IDOUT = -100µA
- 35 V VDD = 5.0V, IHVOUT = +1.0mA,
- 1.0
IDOUT = +100µA
- VPP +1.5V V IOC = +1.0mA
- -30
IOC = -1.0mA
AC Characteristics1 (For VDD = 5.0V, VPP = 300V, TA = 25°C)
Sym Parameter
Min
Max Units Conditions
fCLK
tW
tSU
tH
tWLE
tDLE
tSLE
tON, tOFF
tDHL
tDLH
tr, tf
Clock frequency
Clock width high or low
Data set-up time before clock rises
Data hold time after clock rises
LE pulse width
Delay time clock to LE high to low
LE set-up time before clock rises
Time from LE to HVOUT
Delay time clock to data high to low
Delay time clock to data low to high
All logic inputs
-
62
35
30
80
35
40
-
-
-
-
8.0 MHz ---
- ns ---
- ns ---
- ns ---
- ns ---
- ns ---
- ns ---
4.0 µs CL = 20pF
125 ns CL = 20pF
125 ns CL = 20pF
5.0 ns ---
Note:
1. Shift register speed can be as low as DC as long as data set-up and hold time meet the spec.
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
3


3Pages


HV507PG 電子部品, 半導体
HV507
80-Lead PQFP Package Outline (PG)
20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint
D
D1
E
E1
Note 1
(Index Area
D1/4 x E1/4)
80
1
e
Top View
b
A A2
A1
Side View
View B
Seating
Plane
θ1
L2
L
L1
θ
View B
Gauge
Plane
Seating
Plane
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
A A1 A2 b
D
D1
E
E1 e L L1 L2 θ θ1
Dimen-
sion
(mm)
MIN 2.80* 0.25 2.55 0.30 23.65*
NOM -
- 2.80 - 23.90
MAX 3.40 0.50* 3.05 0.45 24.15*
JEDEC Registration MO-112, Variation CB-1, Issue B, Sept.1995.
* This dimension is not specified in the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-80PQFPPG, Version C041309.
19.80*
20.00
20.20*
17.65*
17.90
18.15*
13.80*
14.00
14.20*
0.80
BSC
0.73
0.88
1.03
1.95
REF
0.25
BSC
0O
3.5O
7O
5O
-
16O
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2010 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
Doc.# DSFP-HV507
A062110
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
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共有リンク

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部品番号部品説明メーカ
HV507PG

64-Channel Serial to Parallel Converter

Supertex  Inc
Supertex Inc
HV507PG-G

64-Channel Serial to Parallel Converter

Supertex
Supertex


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