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HV506X の電気的特性と機能

HV506XのメーカーはSupertex Incです、この部品の機能は「275V 40-Channel Row Driver with SCR Outputs」です。


製品の詳細 ( Datasheet PDF )

部品番号 HV506X
部品説明 275V 40-Channel Row Driver with SCR Outputs
メーカ Supertex Inc
ロゴ Supertex  Inc ロゴ 




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HV506X Datasheet, HV506X PDF,ピン配置, 機能
HV506
275V 40-Channel Row Driver with SCR Outputs
Preliminary
Ordering Information
Device
HV506
80-Lead
Ceramic Gullwing
HV506DG
Package Options
64-Lead 3-Sided
Plastic Gullwing
HV506PG
Die
HV506X
Features
Processed with HVDItechnology
Symmetric row drive
Output voltage up to 275V
Source/Sink current 300mA (min.)
Shift Register Speed 3MHz
Pin-programmable shift direction (DIR)
Hi-Rel processing available
Absolute Maximum Ratings
Logic supply voltage, LVDD1
-0.5V to +15V
Output supply voltage, VDD1
-0.5V to +15V
Substrate bias voltage, Vsub
See Note 3
Output voltage, HVOUT
±300V
Logic input levels
-0.5V to VDD +0.5V
Continuous total power dissipation2 Ceramic
1900mW
Plastic
1200mW
Operating temperature range
Plastic -40°C to +85°C
Ceramic -55°C to +125°C
Storage temperature range
-65°C to +150°C
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
260°C
Notes:
1. All voltages are referenced to V .
SS
2. For operation above 25°C ambient derate linearly to maximum operating
temperture at 20mW/°C for plasitc and at 19mW/°C for ceramic.
3. Vsub must be the most positive with respect to VSS.
General Description
The HV506 is a low-voltage serial to high-voltage parallel con-
verter with push-pull outputs. It is especially suitable for use as
a symmetric row driver in AC thin-film electroluminescent
(ACTFEL) displays.
When the data reset pin (DR ) is at logic high, it will reset all the
IO
outputs of the internal shift register to zero. At the same time, the
output of the shift register will start shifting a logic high from the
least significant bit to the most significant bit. The DR can be
IO
triggered at any time. The DIR pin controls the direction of data
through the device. When DIR is at logic high, DRIOA is the input
and DR is the output. When DIR is grounded, DR is the input
IOB IOB
and the DRIOA is the output. See the Output Sequence Operation
Table for output sequence. The POL and OE pins perform the
polarity select and output enable function respectively. Data is
clocked through the shift register loaded on the low to high
transition of the clock. A logic high in the shift register will cause
the other corresponding output to swing to VDD if POL is high, or
to V if POL is low. All other outputs will be in the High-Z state.
SS
If OE is at logic high all outputs will be in the High-Z state. An
output in the High-Z state may block up to 275V above VSS or
275V below V . The D /D pins are for the positive/negative
DD P N
discharge of the high voltage output HVOUT. Data output buffers
are provided for cascading devices.
LV requires low current for the HV506 logic section. V
DD DD
requires high current for the output section . Typically these two
pins are at the same potential. The same current and potential
conditions apply to the LV , logic, and V , output pins. V must
SS SS
sub
always be equal or greater than the most positive supply.
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and s1pecifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

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HV506X pdf, ピン配列
AC Characteristics
Symbol
Parameter
fCLK
tW (H/L)
tSUD
tHD
tSUC
tSUE
tHC
tHE
tDHL*
tDLH*
tOFF(SCR)
Clock frequency
Pulse width - clock high or low
Data set-up time before clock rises
Data hold time after clock rises
HVOUT delay from clock rises (Hi-Z to H or L)
HVOUT delay from Output Enable rises
HVOUT delay from clock rises (H or L to Hi-Z)
HVOUT delay from Output Enable rises
Delay time clock to data output falls
Delay time clock to data output rises
Turn off time of output SCR
tOFF(D)
Turn off time of output diode
tPOW
tOEW
SR
POL pulse width
Output Enable pulse width
Slew rate of HVOUT
HV506
Min Max Units Conditions
3 MHz
150 ns
50 ns
50 ns
1 µs CL = 10nF
600 ns CL = 10nF
2 µs CL = 10nF
600 ns CL = 10nF
250 ns CL = 15pF
250 ns CL = 15pF
4 µs Time after IOUT 2mA,
CL = 10nF
2 µs Time after IOUT 2mA,
CL = 10nF
3 µs
3 µs
200 V/µs
* The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is
equal to tWH. Therefore the delay is measured from the trailing edge of the clock.
3


3Pages


HV506X 電子部品, 半導体
Functional Block Diagram
VDD
OE
POL
LVDD
DRIOA
CLK
S/R
DIR
HV506
Output
HVOUT1
Output
HVOUT2
DRIOB
LVSS
Function Table
I/O Relations
CLK
Inputs
DIR S/R Data
O/P HIGH
X
X
H
O/P OFF
X
X
L
O/P LOW
X
X
H
O/P OFF
X
X
X
Note:
H = logic high level, L = logic low level, X = irrelevant
POL
H
X
L
X
OE
L
L
L
H
Output
VSS
HVOUT40
DP
DN
HV Outputs
H
HIGH-Z
L
All O/P HIGH-Z
Output Sequence Operation Table
DIR Data Reset In Data Reset Out
L DRIOB
H DRIOA
DRIOA1
DRIOB2
Notes:
1. DRIOA is DRIOBdelayed by 40 clock pulses.
2. DRIOB is DRIOA delayed by 40 clock pulses.
3. Reference to chip layout drawing.
HVOUT # Sequence
40 1
1 40
Direction3
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6 Page



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共有リンク

Link :


部品番号部品説明メーカ
HV506

275V 40-Channel Row Driver with SCR Outputs

Supertex  Inc
Supertex Inc
HV506DG

275V 40-Channel Row Driver with SCR Outputs

Supertex  Inc
Supertex Inc
HV506PG

275V 40-Channel Row Driver with SCR Outputs

Supertex  Inc
Supertex Inc
HV506X

275V 40-Channel Row Driver with SCR Outputs

Supertex  Inc
Supertex Inc


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