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PDF HV310 Data sheet ( Hoja de datos )
| Número de pieza | HV310 | |
| Descripción | Inrush Current Limiter Controllers | |
| Fabricantes | Supertex Inc | |
| Logotipo |  |
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HV310
Hotswap, Inrush Current Limiter Controllers
(Negative Supply Rail)
Features
► PWRGD = Active Low
► -10V to -90V input voltage range
► Few external components
► 0.33mA typical standby supply current
► Programmable over/under voltage limits with
hysteresis
► Programmable current limit
► Active control during all phases of start-up
► Programmable timing
► 8-Lead SOIC package
Applications
► Central office switching
► Servers
► POTS line cards
► ISDN line cards
► xDSL line cards
► PBX Systems
► Powered Ethernet for VoIP
► Distributed power systems
► Negative power supply control
► Antenna and fixed wireless systems
General Description
The Supertex HV310, Hotswap Controller, Negative Supply controls the power
supply connection during insertion of cards or modules into live backplanes.
It may be used in traditional ‘negative 48V’ powered systems or for higher
voltage busses up to negative 90V.
Operation during the initial power up prevents turn-on glitches, and after
complete charging of load capacitors (typically found in filters at the input
of DC-DC converters) the HV310 issues a power good signal. This signal is
typically used to enable the DC-DC converter. Once a PWRGD signal has
been established, the device sleeps in a low power state, important for large
systems with many individual hotswap cards or modules.
An external power MOSFET is required as the pass element, plus a ramp
capacitor, and resistors to establish current limiting and over and under voltage
lockouts. There is no need for additional external snubber components.
Features are programmable over voltage and under voltage detection of the
input voltage which locks out the load connection if the bus (input) voltage
is out of range. An internal voltage regulator creates a stable reference,
and maintains accurate gate drive voltage. The unique control loop scheme
provides full current control and limiting during start up.
Theory of Operation
Initially the external N-channel MOSFET is held off by the gate signal,
preventing an input glitch. After a delay (while internal circuits are activated)
the inrush current to the load is limited by the gate control output. The current
may ramp up and limit at a maximum value programmed by an external
resistor. Initial time delay, to allow for contact bounce, and charging operation
is determined by the single external ramp capacitor connected to the RAMP
pin. When the load capacitor is fully charged, the controller emerges from
current limit mode, an additional time delay occurs before the external N-
channel MOSFET pass transistor is switched to full conduction, and the
PWRGD output signal is activated. The controller will then transition to a low
power standby mode.
Typical Application Circuit
GND
-48V
Long Pin
Jumper
GND
Short Pin
R1
487kΩ
R2
6.81kΩ
R3
9.76kΩ
Long Pin
8
VDD
3 UV
2 OV
RAMP
7
C1
10nF
PWRGD 1
HV310
VEE
4
SENSE GATE
56
ENABLE
+5V
CLOAD
DC/DC
PWM
CONVERTER
COM
NOTES: 1. Undervoltage Shutdown (UV) set to 35V.
2. Overvoltage Shutdown (OV) set to 65V.
3. Remove jumper if short pin is used.
R4
50mΩ
Q1
IRF530
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
1 page  
HV310
Functional Description
Insertion Into Hot Backplanes
Telecom, Data Network and some computer applications
require the ability to insert and remove circuit cards from
systems without powering down the entire system. All cir-
cuit cards have some filter capacitance on the power rails,
which is especially true in circuit cards or network terminal
equipment utilizing distributed power systems. The insertion
can result in high inrush currents that can cause damage to
connector and circuit cards and may result in unacceptable
disturbances on the system backplane power rails.
The HV310 was designed to allow the insertion of these cir-
cuit cards or connection of terminal equipment by eliminat-
ing these inrush currents and powering up these circuits in
a controlled manner after full connector insertion has been
achieved. The HV310 is intended to provide this function on
a negative supply rail in the range of -10 to -90V.
Operation
On initial power application an internal regulator seeks to pro-
vide 10V for the internal IC circuitry. Until the proper internal
voltage is achieved all circuits are held reset, the open drain
PWRGD signal is Hi-Z to inhibit the start of any load circuitry
and the gate to source voltage of the external N-channel
MOSFET is held low. Once the internal under voltage lock
out (UVLO) has been satisfied, the circuit checks the input
supply voltage under voltage (UV) and over voltage (OV)
sense circuits to ensure that the input voltage is within ac-
ceptable programmed limits. These limits are determined by
the selected values of resistors R1, R2 and R3, which form
a voltage divider.
Assuming the above conditions are satisfied and while con-
tinuing to hold the PWRGD output inactive and the external
MOSFET GATE voltage low, the current source feeding the
RAMP pin is turned on. The external capacitor connected to
it begins to charge, thus starting an initial time delay deter-
mined by the value of the capacitor. If an interruption of the
input power occurs during this time (i.e. caused by contact
bounce) or the OV or UV limits are exceeded, an immedi-
ate reset occurs and the external capacitor connected to the
RAMP pin is discharged.
When the voltage on the RAMP pin reaches an internally
set voltage limit, the gate drive circuitry begins to turn on the
external MOSFET; allowing the current to softly rise over a
period of a few hundred micro-seconds to the current limit
set point. While the circuit is limiting current, the voltage on
the RAMP pin will be fixed.
Depending on the value of the load capacitance and the
programmed current limit, charging may continue for some
time. The magnitude of the current limit is programmed by
comparing a voltage developed by a sense resistor connect-
ed between the VEE and SENSE pins to 50mV (Typical).
Once the load capacitor has been charged, the current will
drop which will cause the ramp voltage to continue rising;
providing yet another programmed delay.
When the ramp voltage is within 1.2V of the internally regu-
lated voltage, the controller will force the GATE full on and
will pull the PWRGD pin low and the circuit will transition to a
low power standby mode. The PWRGD pin is often used as
an enable for downstream DC/DC converter loads.
At any time during the start up cycle or thereafter, crossing
the UV and OV limits (including hysteresis) will cause an im-
mediate reset of all internal circuitry. Thereafter the start up
process will begin again.
Application Information
Under Voltage and Over Voltage Detection
The UV and OV pins are connected to comparators with
nominal 1.21V thresholds and 100mV of hysteresis (1.21V
± 50mV). They are used to detect under voltage and over
voltage conditions at the input to the circuit. Whenever the
OV pin rises above its threshold or the UV pin falls below its
threshold the GATE voltage is immediately pulled low, the
PWRGD signal is deactivated and the external capacitor
connected to the RAMP pin is discharged.
The under voltage and over voltage trip points can be pro-
grammed by means of the three resistor divider formed by
R1, R2 and R3. Since the input currents on the UV and OV
pins are negligible the resistor values may be calculated as
follows:
UVOFF = VUVH = 1.16 = |VEEUV| • (R2+R3) / (R1+R2+R3)
OVOFF = VOVL = 1.26 = |VEEOV| • R3 / (R1+R2+R3)
Where |VEEUV| and |VEEOV| are Under & Over Voltage Set
points.
If we select a divider current of 100µA at a nominal operating
input voltage of 50V then:
(R1+R2+R3) = 50V / 100µA = 500kΩ
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HV310.PDF ] | |
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