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PDF HV302 Data sheet ( Hoja de datos )
| Número de pieza | HV302 | |
| Descripción | Sequencing Hotswap Controllers | |
| Fabricantes | Supertex Inc | |
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HV302
HV312
__________________________________________________________________________________________________________________
Initial Release
Sequencing Hotswap Controllers
(Negative Supply Rail)
Features
General Description
-10V to 90V or +10V to +90V Operation
Four PWRGD Flags with Programmable Delays
Integrated “normally-on” Gate Clamp eliminates components
UV/OV Lock Out & Power-On-Reset (POR) for Debouncing
Sense resistor programmed Circuit Breaker & Servo Limit
Programmable Circuit Breaker Delay
Inrush control using either: Servo or Feedback Capacitor
Feedback to RAMP pin saves gate protection components
100ms Start Up Timeout Protection for Output Overload
Programmable Inrush Current di/dt Control
Programmable Auto-Retry (tens of seconds if desired)
Auto-Retry or Latched Operation
Application solution for input voltage step (diode “ORing”)
Enable through Open Drain interface to UV or OV
Low Power, 0.6mA Active Mode, 0.4mA Sleep Mode
Small SOIC-14 Package
Applications
-48V Telecom and Networking
-24V Cellular and Fixed Wireless Systems
-24V PBX Systems
Power Over LAN (IEEE802.3)
Distributed Power Systems
Power Supply Control
+48V Servers and SANs
Hotswap Control of Diode ORed Multiple Power Sources
Cooling Fan Systems
The HV302 and HV312 Hotswap Controllers perform current
limiting, circuit breaker protection, over and under voltage
detection power management functions during insertion of cards or
modules into live backplanes and connectors. They may be used
in systems where active control is implemented in the negative
lead of supplies ranging from -10V to -90V or +10V to +90V.
During initial power application the external pass device is held off
by a “normally-on” circuit that clamps its gate low. Thereafter
UV/OV and power-on-reset work together to suppress gate turn on
due to contact bounce. When stable connection has been
established for the duration of a programmed time delay, the
inrush current is controlled and limited to a programmed level
using one of two possible methods; servo mode or drain to ramp
feedback capacitor mode. When charging of the load capacitor
is completed, the open drain PWRGD-A flag is asserted. Open
drain PWRGD-B, PWRGD-C and PWRGD-D flags are asserted
sequentially after the expiration of their respective programmed
time delays. Thereafter it transitions to a low power sleep mode
and continues to monitor current and input voltage. If full charging
of the load capacitor is not achieved within 100ms or the circuit
breaker is tripped at any time, the external pass device is turned
off and all four PWRGD flags are reset to the inactive state.
Thereafter a programmable auto-retry timer will hold the pass
device off to allow it to cool before resetting and initiating auto-
retry. The auto-retry can be disabled using a single resistor if
desired.
Typical Application Circuit and Waveforms
GND
14
VDD
R1
487k
R2
6.81k
-48V
R3
9.76k
6 UV
5 OV
TB
11
TC
12
________
PWRGD-D / PWRGD-D
________
PWRGD-C /PWRGD-C
________
PWRGD-B / PWRGD-B
________
PWRGD-A / PWRGD-A
1
2
3
4
HV302 / HV312
Cload
TD RAMP VEE SENSE GATE
13 10
7
8
9
100uF
RTB
RTC
RTD
C1
10nF
R4
0.0125
NOTES:
1. Under Voltage Shutdown (UV) set to 35V.
2. Over Voltage Shutdown (OV) set to 65V.
3. Current Limit set to -1A.
4. Circuit Breaker set to 8A.
C2
0.75nF
Q1
IRF530
___
EN / EN
DC/DC PWM
CONVERTER
-12V
COM
___
EN / EN
DC/DC PWM
CONVERTER
+12V
COM
___
EN / EN
DC/DC PWM
CONVERTER
+5V
COM
___
EN / EN
DC/DC PWM
CONVERTER
+3.3V
COM
1 Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
1 page  
Functional Description - continued
In Feedback Capacitor Mode operation, assuming the UV and
OV limits are satisfied and while continuing to hold the PWRGD
flags inactive and the external MOSFET GATE voltage low, the
current source feeding the RAMP pin is turned on. The external
ramp capacitor (CRAMP) begins to charge and the feedback
capacitor (CFB) begins to discharge, thus starting an initial time
delay determined by the equivalent value of the capacitors and the
2Vbg threshold voltage of the RAMP pin. During this time if the
OV or UV limits are exceeded, an immediate reset occurs, the
ramp capacitor is discharged and the feedback capacitor is
recharged.
When the voltage on the RAMP pin exceeds the 2Vbg threshold
voltage, the gate drive circuit begins to apply voltage to the gate of
the external MOSFET, which begins to turn on when its gate
threshold voltage is reached. However, the source current from
the RAMP pin limits the dv/dt of the feedback capacitor (CFB)
which, in turn, programs the inrush current limit (ICL) in accordance
with the relationship ICL= IRAMP x CLOAD/CFB and thus the dv/dt of the
load capacitor. At this point essentially all available current from
the RAMP pin flows into the feedback capacitor, thus the voltage
on the ramp capacitor and the RAMP pin remains essentially
constant, thereby limiting and controlling the gate voltage of the
external MOSFET (See Programming Current Limit and Circuit
Breaker in Design Information section). When the load capacitor is
fully charged the current flowing into the feedback capacitor is
reduced and the voltage drop across the MOSFET essentially
drops to zero, effectively connecting the feedback capacitor in
parallel with the ramp capacitor. Now the current from the RAMP
pin flows into the parallel-connected capacitors and the voltage on
the RAMP pin begins to rise, thereby providing yet another
programmed delay.
HV302 / HV312
Whether operating in Servo Mode or Feedback Capacitor Mode,
when the ramp voltage is within 1.2V of the regulated internal
supply voltage, the controller will force the GATE terminal to a
nominal 10V, the PWRGD-A pin will change to an active state and
the Circuit Breaker is enabled. PWRGD-B will change to an active
state a programmed delay time after PWRGD-A went active,
PWRGD-C will change to an active state a programmed delay time
after PWRGD-B went active, PWRGD-D will change to an active
state a programmed delay time after PWRGD-C went active and
the circuit transitions to a low power sleep mode. While in sleep
mode the circuit continues to monitor the current and the OV and
UV status.
When the voltage on the SENSE pin rises to 100mV, indicating an
over current condition, the circuit breaker will trip in less than 5µs.
This time may be extended by the addition of external
components.
If due to output overload conditions during startup full charging of
the load is not achieved within 100ms or a load fault occurs at any
time the circuit breaker is tripped, the MOSFET is turned off by
pulling down the GATE to VEE and all four PWRGD flags are reset.
Thereafter an auto-retry timer, programmed by the capacitor
connected to the RAMP pin, will hold the pass device off to allow it
to cool before resetting and restarting. The auto-retry can be
disabled using a single resistor if desired (See Auto-Retry and
Auto-Retry Disable in Design Information section).
At any time during the start up cycle or thereafter, crossing the UV
and OV limits (including hysteresis) will cause an immediate reset
of all internal circuitry. When the input supply voltage returns to a
value within the programmed UV and OV limits a new start up
sequence will be immediately initiated.
5 Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet HV302.PDF ] | |
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