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Datasheet HV209 PDF ( 特性, スペック, ピン接続図 )

部品番号 HV209
部品説明 12-Channel High Voltage Analog Switch
メーカ Supertex Inc
ロゴ Supertex  Inc ロゴ 
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HV209 Datasheet, HV209 PDF,ピン配置, 機能
Supertex inc.
HV209
12-Channel
High Voltage Analog Switch
Features
►HVCMOS® technology for high performance
►Operating voltage of up to 200V
Output on-resistance typically 22Ω
►Integrated bleed resistors on the outputs
►5.0V to 12.0V CMOS logic compatibility
►Very low quiescent current consumption (-10µA)
►-58dB typical off isolation at 5.0MHz
►Low parasitic capacitance
►Excellent noise immunity
►Flexible high voltage supplies
Block Diagram
D
LE
CL
General Description
The Supertex HV209 is a 200V low charge injection 12-channel
high voltage analog switch configured as 6 SPDT analog switches
intended for medical ultrasound applications.
Bleed resistors are integrated on the output switches to eliminate
charge built up on the piezo electric transducers.The bleed resistors
are at a nominal value of 35kΩ. Using HVCMOS technology, this
device combines high voltage bilateral DMOS switches and low
power CMOS logic to provide efficient control of high voltage
analog signals. The outputs are configured as single-pole double-
throw analog switches. Data is shifted into a 6-bit shift register
using an external clock. The LE latches the shift register data into
the individual switch latches. A logic HI connects a switch common
YX to SWX. A logic LOW connects YX to SWX. A logic HI in CL resets
all switches to SWX simultaneously.
VPP VNN
High Voltage
Level
Translator
SW0
Y0
SW0
VDD
CLK
DIN
DOUT
GND
6 BIT
SHIFT
REGISTER
D High Voltage
LE Level
CL Translator
D High Voltage
LE Level
CL Translator
D High Voltage
LE Level
CL Translator
SW1
Y1
SW1
SW2
Y2
SW2
SW3
Y3
SW3
D High Voltage
LE Level
CL Translator
D
LE
CL
LE CL
High Voltage
Level
Translator
SW4
Y4
SW4
SW5
Y5
SW5
RGND1/RGND2
Doc.# DSFP-HV209
B070213
Supertex inc.
www.supertex.com

1 Page



HV209 pdf, ピン配列
HV209
DC Electrical Characteristics
(over recommended operating conditions unless otherwise noted)
Sym Parameter
0OC +25OC
min max min typ max
- 30 - 26 38
- 25 - 22 27
RONS
Small signal switch
on-resistance
- 25 - 22 27
- 18 - 18 24
- 23 - 20 25
ΔRONS
RONL
RINT
VOS
Small signal switch
on-resistance matching
Large signal switch
on-resistance
Output switch shunt
resistance
DC offset switch off
DC offset switch on
- 22 - 16 25
- 20 - 5.0 20
- - - 15 -
- - 20 35 50
- 50 -
- 50 -
- 50
- 50
IPPQ Pos. HV supply current
INNQ Neg. HV supply current
IPPQ Pos. HV supply current
INNQ Neg. HV supply current
ISW
Switch output peak
current
- - - 10 50
- - - -10 -50
- - - 10 50
- - - -10 -50
- 3.0 - 3.0 2.0
fSW Output switch frequency - - - - 50
- 6.5 -
- 7.0
IPP IPP supply current
- 4.0 -
- 4.0 -
- 5.0
- 5.0
- 6.5 -
- 7.0
INN INN supply current
- 4.0 -
- 5.0
- 4.0 -
- 5.0
IDD
Logic supply average
current
- 4.0 -
- 4.0
IDDQ
Logic supply quiescent
current
- 10 -
- 10
ISOR Data out source current 0.45 - 0.45 0.70 -
ISINK Data out sink current
0.45 - 0.45 0.70 -
CIN Logic input capacitance
- 10 -
- 10
+70OC
min max
- 48
- 32
- 30
- 27
30
27
- 20
--
--
- 50
- 50
--
--
--
--
- 2.0
-
- 8.0
- 5.5
- 5.5
- 8.0
- 5.5
- 5.5
- 4.0
- 10
0.40 -
0.40 -
- 10
Units
Ω
%
Ω
mV
mV
µA
µA
A
KHz
mA
mA
mA
µA
mA
mA
pF
Conditions
ISIG = 5.0mA
ISIG = 200mA
VPP = 40V
VNN = -160V
ISIG = 5.0mA
ISIG = 200mA
VPP = 100V
VNN = -100V
ISIG = 5.0mA
ISIG = 200mA
VPP = 190V
VNN = -10V
ISW = 5.0mA, VPP = 100V,
VNN = -100V
VSIG = VPP -10V, ISIG = 1.0A
Output switch to RGND
IRINT = 0.5mA
No load, RGND = 0V
No load, RGND = 0V
All SWs off
All SWs on, ISW = 5.0mA
VSIG duty cycle ≤ 0.1%
Duty cycle = 50%
VPP = 40V
VNN = -160V
VPP = 100V
VNN = -100V
VPP = 190V
VNN = -10V
VPP = 40V,
VNN = -160V
VPP = 100V
VNN = -100V
VPP = 190V
VNN = -10V
50KHz
output
switching
frequency
with no load
50KHz
output
switching
frequency
with no load
fCLK = 5.0MHz, VDD = 5.0V
---
VOUT = VDD -0.7V
VOUT = 0.7V
---
Doc.# DSFP-HV209
B070213
Supertex inc.
3 www.supertex.com


3Pages


HV209 電子部品, 半導体
Logic Timing Waveforms
DN+1
DN
DATA
IN
50%
50%
DN-1
HV209
LE
CLOCK
DATA
OUT
VOUT
(typ)
OFF
ON
50%
tSU
50%
tWLE
tSD
50%
tH
tDO
50%
tOFF
90%
50%
tON
10%
CLR
50%
tWCL
Logic Truth Table
Data Inputs
D0 D1 D2 D3
L
H
L
H
L
H
L
H
D4
L
H
XXXXX
XXXXX
50%
LE
D5
L
L
L
L
L
L
L
L
L
L
LL
HL
XH
XX
Switch States
CL
Y0 Y1 Y2 Y3 Y4 Y5
L SW0
L SW0
L SW1
L SW1
L SW2
L SW2
L SW3
L SW3
L SW4
L SW4
L SW5
L SW5
L Hold Previous State
H SW0 SW1 SW2 SW3 SW4 SW5
Doc.# DSFP-HV209
B070213
Supertex inc.
6 www.supertex.com

6 Page





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