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PDF HUF76432P3 Data sheet ( Hoja de datos )
| Número de pieza | HUF76432P3 | |
| Descripción | 55A/ 60V/ 0.019 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFET | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
HUF76609D3, HUF76609D3S
October 1999 File Number 4688.2
10A, 100V, 0.165 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
SOURCE
HUF76609D3
HUF76609D3S
Symbol
D
G
S
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.160Ω, VGS = 10V
- rDS(ON) = 0.165Ω, VGS = 5V
• Simulation Models
- Temperature Compensated PSPICE® and SABER©
Electrical Models
- Spice and SABER© Thermal Impedance Models
- www.Intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Switching Time vs RGS Curves
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76609D3
TO-251AA
76609D
HUF76609D3S
TO-252AA
76609D
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76609D3ST.
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
HUF76609D3,
HUF76609D3S
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous
Continuous
Continuous
(TC=
(TC=
(TC=
211500o00CooCC, V,, VVGGGSSS===1054VV.5))V().F.(igF.ui.gr.ue.r2e. ).2..)
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ID
ID
ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
100
100
±16
10
10
7
7
Figure 4
Figures 6, 17, 18
V
V
V
A
A
A
A
Power Dissipation . . .
Derate Above 25oC
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PD
...
49
0.327
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 175
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300 oC
260 oC
NOTE:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1 CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy Inc.http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
HUF76609D3, HUF76609D3S
Typical Performance Curves (Continued)
1.2 1.2
VGS = VDS, ID = 250µA
ID = 250µA
1.0
1.1
0.8
1.0
0.6
0.4
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
2000
1000
100
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
10
VGS = 0V, f = 1MHz
5
0.1 1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
0.9
-80
-40 0
40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
VDD = 50V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
2 ID = 10A
ID = 7A
ID = 4A
0
0 3 6 9 12 15
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
80
VGS = 4.5V, VDD = 50V, ID = 7A
60
td(OFF)
40
tr
tf
20
0
0
td(ON)
10 20 30 40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
120
VGS = 10V, VDD = 50V, ID = 10A
90
td(OFF)
60
tf
30
0
0
tr
td(ON)
10 20 30 40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HUF76432P3.PDF ] | |
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