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Número de pieza | HUF76419P3 | |
Descripción | 27A/ 60V/ 0.040 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFET | |
Fabricantes | Intersil Corporation | |
Logotipo | ||
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No Preview Available ! Data Sheet
HUF76419P3, HUF76419S3S
August 1999 File Number 4669.1
27A, 60V, 0.040 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
Packaging
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN
(FLANGE)
HUF76419P3
GATE
SOURCE
HUF76419S3S
Symbol
D
G
S
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.035Ω, VGS = 10V
- rDS(ON) = 0.040Ω, VGS = 5V
• Simulation Models
- Temperature Compensated PSPICE® and SABER©
Electrical Models
- Spice and SABER© Thermal Impedance Models
- www.Intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Switching Time vs RGS Curves
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76419P3
TO-220AB
76419P
HUF76419S3S
TO-263AB
76419S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76419S3ST.
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
HUF76419P3,
HUF76419S3S
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous
Continuous
Continuous
(TC=
(TC=
(TC=
211500o00CooCC, V,, VVGGGSSS===1054VV.5))V().F.(igF.ui.gr.ue.r2e. ).2..)
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ID
ID
ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
60
60
±16
27
29
19
18
Figure 4
Figures 6, 17, 18
V
V
V
A
A
A
A
Power Dissipation . . .
Derate Above 25oC
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PD
...
75 W
0.5 W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 175
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300 oC
260 oC
NOTES:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
4-1 CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE™ is a registered trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy Inc. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page HUF76419P3, HUF76419S3S
Typical Performance Curves (Continued)
1.2
VGS = VDS, ID = 250µA
1.0
0.8
0.6
0.4
-80
-40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
2000
1000
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
10
0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
60
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
1.2
ID = 250µA
1.1
1.0
0.9
-80
-40 0
40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
VDD = 30V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
2 ID = 29A
ID = 19A
ID = 10A
0
0 5 10 15 20 25
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
250
VGS = 4.5V, VDD = 30V, ID = 18A
200
tr
150
100
50
0
0
tf
td(OFF)
td(ON)
10 20 30 40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
150
VGS = 10V, VDD = 30V, ID = 29A
100
tf
tr
50
0
0
td(OFF)
td(ON)
10 20 30 40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
4-5
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet HUF76419P3.PDF ] |
Número de pieza | Descripción | Fabricantes |
HUF76419P3 | 27A/ 60V/ 0.040 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFET | Fairchild Semiconductor |
HUF76419P3 | 27A/ 60V/ 0.040 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFET | Intersil Corporation |
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