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PDF HUF76131SK8 Data sheet ( Hoja de datos )

Número de pieza HUF76131SK8
Descripción 10A/ 30V/ 0.013 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFET
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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TM
Data Sheet
HUF76131SK8
June 2000 File Number 4396.5
10A, 30V, 0.013 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
This N-Channel power MOSFET is
® manufactured using the innovative
UltraFET process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA76131.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76131SK8
MS-012AA
76131SK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76131SK8T.
Features
• Logic Level Gate Drive
• 10A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.013
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
SOURCE(1)
DRAIN(8)
SOURCE(2)
DRAIN(7)
SOURCE(3)
DRAIN(6)
GATE(4)
DRAIN(5)
Packaging
JEDEC MS-012AA
BRANDING DASH
1
2
3
4
5
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET® is a registered trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2000.

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HUF76131SK8 pdf
HUF76131SK8
Typical Performance Curves (Continued)
2500
2000
1500
CISS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
10
8
6
1000
500
0
0
COSS
CRSS
5 10 15 20 25
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
4
WAVEFORMS IN
DESCENDING ORDER:
2
ID = 20A
ID = 10A
VDD = 15V
ID = 5A
ID = 2.5A
0
0 10 20 30 40 50
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes 7254 and 7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
80
60
ID = 5A
40 ID = 2.5A
ID = 10A
ID = 20A
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0 2 4 6 8 10
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 14. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
200
VDD = 15V, ID = 10A, RL= 1.5
150
100
tr
td(OFF)
tf
50
td(ON)
0
0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
5

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