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HUF76129S3S の電気的特性と機能

HUF76129S3SのメーカーはFairchild Semiconductorです、この部品の機能は「56A/ 30V/ 0.016 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFETs」です。


製品の詳細 ( Datasheet PDF )

部品番号 HUF76129S3S
部品説明 56A/ 30V/ 0.016 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFETs
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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HUF76129S3S Datasheet, HUF76129S3S PDF,ピン配置, 機能
Data Sheet
HUF76129P3, HUF76129S3S
January 2003
56A, 30V, 0.016 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET™ process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA76129.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76129P3
TO-220AB
76129P
HUF76129S3S
TO-263AB
76129S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF76129S3ST.
Packaging
DRAIN
(FLANGE)
JEDEC TO-220AB
SOURCE
DRAIN
GATE
Features
• Logic Level Gate Drive
• 56A, 30V
Ultra Low On-Resistance, rDS(ON) = 0.016
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER© Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
©2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1

1 Page





HUF76129S3S pdf, ピン配列
HUF76129P3, HUF76129S3S
Electrical Specifications TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
tf
Turn-Off Time
tOFF
GATE CHARGE SPECIFICATIONS
VDD = 15V, ID 56A,
RL = 0.268, VGS = 10V,
RGS = 8.2
(Figures 16, 21, 22)
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Qg(TOT)
Qg(5)
Qg(TH)
Qgs
Qgd
VGS = 0V to 10V
VGS = 0V to 5V
VGS = 0V to 1V
VDD = 15V,
ID 35A,
RL = 0.429
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
CISS
COSS
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
VSD
trr
QRR
ISD = 35A
ISD = 35A, dISD/dt = 100A/µs
ISD = 35A, dISD/dt = 100A/µs
MIN TYP MAX UNITS
- - 62 ns
- 11 - ns
- 30 - ns
- 68 - ns
- 35 - ns
- - 155 ns
- 37 45 nC
- 19 23 nC
- 1.4 1.7 nC
- 4.50 -
nC
- 10.30 -
nC
- 1350 -
- 700 -
- 160 -
pF
pF
pF
MIN TYP MAX UNITS
- - 1.25 V
- - 60 ns
- - 105 nC
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
0 25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
60
50
VGS = 10V
40
VGS = 4.5V
30
20
10
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
©2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1


3Pages


HUF76129S3S 電子部品, 半導体
HUF76129P3, HUF76129S3S
Typical Performance Curves (Continued)
2000
1600
1200
800
CISS
COSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
400
0
0
CRSS
5 10 15 20 25
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
400
VGS = 4.5V, VDD = 15V, ID = 34A, RL = 0.441
tr
300
200
tf
100 td(ON) td(OFF)
0
0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
10
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
2 ID = 56A
ID = 35A
ID = 20A
0
0 10 20 30 40
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes 7254 and 7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
300
VGS = 10V, VDD = 15V, ID = 56A, RL = 0.268
250
td(OFF)
200
150 tf
100
50
0
0
tr
td(ON)
10 20 30 40
RGS, GATE TO SOURCE RESISTANCE ()
50
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
©2003 Fairchild Semiconductor Corporation
HUF76129P3, HUF76129S3S Rev. B1

6 Page



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部品番号部品説明メーカ
HUF76129S3S

56A/ 30V/ 0.016 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFETs

Fairchild Semiconductor
Fairchild Semiconductor
HUF76129S3S

56A/ 30V/ 0.016 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFETs

Intersil Corporation
Intersil Corporation


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