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HUF76129D3のメーカーはFairchild Semiconductorです、この部品の機能は「20A/ 30V/ 0.016 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFETs」です。 |
部品番号 | HUF76129D3 |
| |
部品説明 | 20A/ 30V/ 0.016 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFETs | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとHUF76129D3ダウンロード(pdfファイル)リンクがあります。 Total 11 pages
Data Sheet
HUF76129D3, HUF76129D3S
January 2003
20A, 30V, 0.016 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET™ process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA76129.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76129D3
TO-251AA
76129D
HUF76129D3S
TO-252AA
76129D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF76129D3ST.
Packaging
JEDEC TO-251AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
Features
• Logic Level Gate Drive
• 20A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.016Ω
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER© Mode
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-252AA
GATE
SOURCE
DRAIN
(FLANGE)
©2003 Fairchild Semiconductor Corporation
HUF76129D3, HUF76129D3S Rev. B1
1 Page HUF76129D3, HUF76129D3S
Electrical Specifications TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
tON
td(ON)
tr
td(OFF)
tf
tOFF
VDD = 15V, ID ≅ 20A, RL = 0.75Ω,
VGS = 10V, RGS = 10Ω
(Figures 16, 21, 22)
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Chatge
CAPACITANCE SPECIFICATIONS
Qg(TOT)
Qg(5)
Qg(TH)
Qgs
Qgd
VGS = 0V to 10V
VGS = 0V to 5V
VGS = 0V to 1V
VDD = 15V, ID ≅ 20A,
RL = 0.75Ω
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
CISS
COSS
CRSS
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PARAMETER
SYMBOL
TEST CONDITIONS
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
VSD
trr
QRR
ISD = 20A
ISD = 20A, dISD/dt = 100A/µs
ISD = 20A, dISD/dt = 100A/µs
Typical Performance Curves
MIN
-
-
-
TYP
-
7
47
60
54
-
38
22
1.4
3.70
11.20
1425
720
170
TYP
-
-
-
MAX UNITS
80 ns
- ns
- ns
- ns
- ns
110 ns
46 nC
26 nC
1.7 nC
- nC
- nC
- pF
- pF
- pF
MAX
1.25
72
107
UNITS
V
ns
nC
1.2
1.0
0.8
0.6
0.4
0.2
0
0 25 50 75 100 125 150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
©2003 Fairchild Semiconductor Corporation
25
20
15 VGS=10V
10 VGS=4.5V
5
0
25
50 75 100 125
TC, CASE TEMPERATURE (oC)
150
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
HUF76129D3, HUF76129D3S Rev. B1
3Pages HUF76129D3, HUF76129D3S
Typical Performance Curves (Continued)
2000
1600
1200
800
CISS
COSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
400
0
0
CRSS
5 10 15 20 25
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
2 ID = 20A
ID = 10A
ID = 2A
0
0 10 20 30 40
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes 7254 and 7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
500
VGS = 4.5V, VDD = 15V, ID = 20A, RL= 0.75Ω
400
tr
300
td(OFF) tf
200
100
0
0
td(ON)
10 20 30 40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
300
VGS = 10V, VDD = 15V, ID = 20A, RL= 0.75Ω
250
td(OFF)
200
tf
150
100
50
0
0
tr
td(ON)
10 20 30 40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01Ω
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
©2003 Fairchild Semiconductor Corporation
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
HUF76129D3, HUF76129D3S Rev. B1
6 Page | |||
ページ | 合計 : 11 ページ | ||
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部品番号 | 部品説明 | メーカ |
HUF76129D3 | 20A/ 30V/ 0.016 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFETs | Fairchild Semiconductor |
HUF76129D3 | 20A/ 30V/ 0.016 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFETs | Intersil Corporation |
HUF76129D3S | 20A/ 30V/ 0.016 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFETs | Fairchild Semiconductor |
HUF76129D3S | 20A/ 30V/ 0.016 Ohm/ N-Channel/ Logic Level UltraFET Power MOSFETs | Intersil Corporation |