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HUF76113DK8のメーカーはFairchild Semiconductorです、この部品の機能は「6A/ 30V/ 0.032 Ohm/ Dual N-Channel/ Logic Level UltraFET Power MOSFET」です。 |
部品番号 | HUF76113DK8 |
| |
部品説明 | 6A/ 30V/ 0.032 Ohm/ Dual N-Channel/ Logic Level UltraFET Power MOSFET | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとHUF76113DK8ダウンロード(pdfファイル)リンクがあります。 Total 12 pages
Data Sheet
HUF76113DK8
January 2003
6A, 30V, 0.032 Ohm, Dual N-Channel,
Logic Level UltraFET Power MOSFET
This N-Channel power MOSFET is
® manufactured using the innovative
UltraFET process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators, switching
converters, motor drivers, relay drivers, low-voltage bus
switches, and power management in portable and battery-
operated products.
Formerly developmental type TA76113.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76113DK8
MS-012AA
76113DK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76113DK8T.
Features
• Logic Level Gate Drive
• 6A, 30V
• Ultra Low On-Resistance, rDS(ON) = 0.032Ω
• Temperature Compensating PSPICE® Model
• Temperature Compensating SABER™ Model
• Thermal Impedance SPICE Model
• Thermal Impedance SABER Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
S1(1)
G1(2)
D1(8)
D1(7)
S2(3)
G2(4)
D2(6)
D2(5)
Packaging
JEDEC MS-012AA
BRANDING DASH
1
2
3
4
5
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
1 Page HUF76113DK8
Electrical Specifications TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
td(OFF)
Fall Time
tf
Turn-Off Time
tOFF
GATE CHARGE SPECIFICATIONS
VDD = 15V, ID ≅ 6A, RL = 2.5Ω, VGS =
10V,
RGS = 18Ω
(Figure 16)
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Qg(TOT)
Qg(5)
Qg(TH)
Qgs
Qgd
VGS = 0V to 10V
VGS = 0V to 5V
VGS = 0V to 1V
VDD = 15V, ID ≅ 1.8A,
RL = 8.3Ω
Ig(REF) = 1.0mA
(Figure 14)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
CISS
COSS
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
VSD
trr
QRR
ISD = 6A
ISD = 1.8A
ISD = 1.8A, dISD/dt = 100A/µs
ISD = 1.8A, dISD/dt = 100A/µs
Typical Performance Curves
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MIN
-
-
-
TYP
-
6.5
33
50
40
-
16.0
8.4
0.55
1.50
3.90
605
275
40
TYP
-
-
-
MAX UNITS
60 ns
- ns
- ns
- ns
- ns
135 ns
19.2
nC
10.2
nC
0.66
nC
- nC
- nC
- pF
- pF
- pF
MAX
1.25
1.00
40
42
UNITS
V
V
ns
nC
1.2
1.0
0.8
0.6
0.4
0.2
0
0 25 50 75 100 125 150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
7
6
VGS = 10V, RθJA = 50oC/W
5
4
3
2
VGS = 4.5V, RθJA = 228oC/W
1
0
25 50 75 100 125 150
TA, AMBIENT TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
3Pages HUF76113DK8
Typical Performance Curves (Continued)
1000
800
600
CISS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
10
VDD = 15V
8
6
400
200
0
0
COSS
CRSS
5 10 15 20 25
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
120
VGS = 4.5V, VDD = 15V, ID = 1.7A, RL= 8.8Ω
90
tr
tf
60
td(OFF)
30
td(ON)
0
0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
4
WAVEFORMS IN
2 DESCENDING ORDER:
ID = 6A
ID = 1.8A
0
0 5 10 15 20
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
150
VGS = 10V, VDD = 15V, ID = 6A, RL= 2.5Ω
120
90
60
td(OFF)
tf
tr
30
0
0
td(ON)
10 20 30 40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01Ω
0
tP
IAS
BVDSS
VDS
VDD
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
©2003 Fairchild Semiconductor Corporation
HUF76113DK8 Rev. B1
6 Page | |||
ページ | 合計 : 12 ページ | ||
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部品番号 | 部品説明 | メーカ |
HUF76113DK8 | 6A/ 30V/ 0.032 Ohm/ Dual N-Channel/ Logic Level UltraFET Power MOSFET | Fairchild Semiconductor |
HUF76113DK8 | 6A/ 30V/ 0.032 Ohm/ Dual N-Channel/ Logic Level UltraFET Power MOSFET | Intersil Corporation |