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PDF HUF76013D3S Data sheet ( Hoja de datos )

Número de pieza HUF76013D3S
Descripción 20A/ 20V/ 0.022 Ohm/ N-Channel/ Logic Level Power MOSFETs
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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Data Sheet
HUF76009P3, HUF76009D3S
December 2001
20A, 20V, 0.027 Ohm, N-Channel, Logic
Level Power MOSFETs
THE HUF76009 is an application-specific MOSFET
optimized for switching when used as the upper switch in
synchronous buck applications. The low gate charge and low
input capacitance results in lower driver and lower switching
losses thereby increasing the overall system efficiency.
Symbol
D
G
S
Packaging
HUF76009D3S
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
HUFD76009P3
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
Features
• 20A, 20V
- rDS(ON) = 0.027Ω, VGS = 10V
- rDS(ON) = 0.039Ω, VGS = 5V
• PWM optimized for synchronous buck applications
• Fast Switching
• Low Gate Charge
- Qg Total 11nC (Typ)
• Low Capacitance
- CISS 470pF (Typ)
- CRSS 50pF (Typ)
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF76009P3
TO-220AB
76009P
HUF76009D3S
TO-252AA
76009D
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the HUF76009D3S in tape and reel, e.g., HUF76009D3ST.
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
SYMBOL
PARAMETER
HUF76009P3,
HUF76009D3S
UNITS
VDSS
VDGR
VGS
ID
ID
IDM
PD
Drain to Source Voltage (Note 1)
Drain to Gate Voltage (RGS = 20k) (Note 1)
Gate to Source Voltage
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2)
Continuous (TC = 100oC, VGS = 5V)
Pulsed Drain Current
Power Dissipation
Derate Above 25oC
TJ, TSTG
Operating and Storage Temperature
Maximum Temperature for Soldering
TL
Tpkg
Leads at 0.063in (1.6mm) from Case for 10s
Package Body for 10s, See Techbrief TB334
THERMAL SPECIFICATIONS
RθJC
RθJA
Thermal Resistance Junction to Case, TO-220, TO-252
Thermal Resistance Junction to Ambient TO-220
Thermal Resistance Junction to Ambient TO-252
20
20
±16
20
16
Figure 4
41
0.33
-55 to 150
300
260
3.04
62
100
V
V
V
A
A
A
W
W/oC
oC
oC
oC
oC/W
oC/W
oC/W
NOTE:
1. TJ = 25oC to 125oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
©2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B

1 page




HUF76013D3S pdf
HUF76009P3, HUF76009D3S
Typical Performance Curves (Continued)
1.2
ID = 250µA
1.1
1.0
0.9
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
VDD = 10V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
2 ID = 16A
ID = 10A
ID = 5A
0
0 3 6 9 12
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
2000
1000
COSS CDS + CGD
CISS = CGS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
50
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
20
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
150
VGS = 5V, VDD = 10V, ID = 16A
125
100
tr
75
50 tf
td(OFF)
25
td(ON)
0
0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
©2001 Fairchild Semiconductor Corporation
100
80
VGS = 10V, VDD = 10V, ID = 20A
60
tr
td(OFF)
40
20
0
0
tf
td(ON)
10 20 30 40
RGS, GATE TO SOURCE RESISTANCE ()
50
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
HUF76009P3, HUF76009D3S Rev. B

5 Page





HUF76013D3S arduino
HUF76009P3, HUF76009D3S
TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
ØP E
A
Q
H1
D
E1
L1
L
60o
D1
b1
b
45o
c
12
e
e1
3
J1
A1
TERM. 4
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.170
0.180
4.32
4.57
-
A1
0.048
0.052
1.22
1.32
-
b
0.030
0.034
0.77
0.86
3, 4
b1
0.045
0.055
1.15
1.39
2, 3
c
0.014
0.019
0.36
0.48 2, 3, 4
D
0.590
0.610 14.99
15.49
-
D1 - 0.160 - 4.06
E
0.395
0.410 10.04
10.41
-
-
E1
- 0.030 - 0.76
-
e 0.100 TYP
2.54 TYP
5
e1 0.200 BSC
5.08 BSC
H1
0.235
0.255
5.97
6.47
J1
0.100
0.110
2.54
2.79
L
0.530
0.550 13.47
13.97
5
-
6
-
L1
0.130
0.150
3.31
3.81
ØP
0.149
0.153
3.79
3.88
2
-
Q
0.102
0.112
2.60
2.84
-
NOTES:
1. These dimensions are within allowable dimensions of Rev. J of
JEDEC TO-220AB outline dated 3-24-87.
2. Lead dimension and finish uncontrolled in L1.
3. Lead dimension (without solder).
4. Add typically 0.002 inches (0.05mm) for solder coating.
5. Position of lead to be measured 0.250 inches (6.35mm) from bot-
tom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from bot-
tom of dimension D.
7. Controlling dimensio n :Inch.
8. Revision 2 dated 7-97.
©2001 Fairchild Semiconductor Corporation
HUF76009P3, HUF76009D3S Rev. B

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